SPC5121YVY400BR Freescale, SPC5121YVY400BR Datasheet - Page 58

• Manufacturer Part Number: SPC5121YVY400BR
• Manufacturer: Freescale

Specifications of SPC5121YVY400BR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Electrical and Thermal Characteristics
3.3.12
This section specifies the USB ULPI timing.
For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004.
58
1
2
Sym
MDC is generated by MPC5121e/MPC5123 with a duty cycle of 50% except when MII_SPEED in the FEC
MII_SPEED control register is changed during operation. See the MPC5121e/MPC5123 Reference Manual.
The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII
characteristic) by programming the FEC MII_SPEED control register. See the MPC5121e/MPC5123 Reference
Manual.
t
t
t
t
t
t
10
11
12
13
14
15
MDC falling edge to MDIO output delay
MDIO (input) to MDC rising edge setup
MDIO (input) to MDC rising edge hold
MDC pulse width high
MDC pulse width low
MDC period
USB ULPI
MDIO (Output)
MDC (Output)
MDIO (Input)
2
Figure 37. Ethernet Timing Diagram – MII Serial Management
Table 34. MII Serial Management Channel Signal Timing
Description
1
1
MPC5121E/MPC5123 Data Sheet, Rev. 3
t
11
t
12
t
13
t
15
t
10
Min
160
160
400
10
t
0
0
14
Max
25
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
SpecID
A11.10
A11.11
A11.12
A11.13
A11.14
A11.15