SPC5121YVY400BR Freescale, SPC5121YVY400BR Datasheet

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... BDLC – J1850 interface • VIU – Video Input, ITU-656 compliant • RTC – On-Chip real-time clock This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009. All rights reserved. ...

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... Pull-Up/Pull-Down Resistor Requirements . . . . . . . . . 77 4.4.1 Pull-Down Resistor Requirements for TEST pin 77 4.4.2 Pull-Up Requirements for the PCI Control Lines77 4.5 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.1 TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.2 e300 COP/BDM Interface . . . . . . . . . . . . . . . . 78 5 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2 Mechanical Dimensions Product Documentation MPC5121E/MPC5123 Data Sheet, Rev Freescale Semiconductor ...

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... Figure 1. Simplified MPC5121e/MPC5123 Block Diagram 1 Ordering Information Freescale Part Speed (MHz) Number MPC5121VY400B 400 MPC5121VY400BR 400 MPC5121YVY400B 400 MPC5121YVY400BR 400 SPC5121YVY400B 400 SPC5121YVY400BR 400 Freescale Part Speed (MHz) Number MPC5123VY300B 300 MPC5123VY300BR 300 MPC5123YVY300B 300 MPC5123YVY300BR 300 Freescale Semiconductor Display DDR1/2 Memory ...

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... RoHS and Pb-free Tape and Reel Tray Power Supply Notes VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — Freescale Semiconductor ...

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... MDM0 MDM1 MDM2 MDM3 MDQS0 MDQS1 MDQS2 MDQS3 MBA0 MBA1 MBA2 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 Freescale Semiconductor Pad Type AD10 DDR AF12 DDR AD11 DDR AB12 DDR AD12 DDR AB13 DDR AF14 DDR AD13 DDR AE13 DDR ...

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... VDD_MEM_IO — VDD_MEM_IO — VDD_MEM_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — Freescale Semiconductor ...

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... EMB_AD13 EMB_AD12 EMB_AD11 EMB_AD10 EMB_AD09 EMB_AD08 EMB_AD07 EMB_AD06 EMB_AD05 EMB_AD04 EMB_AD03 EMB_AD02 EMB_AD01 EMB_AD00 PATA_CE1 PATA_CE2 PATA_ISOLATE PATA_IOR PATA_IOW PATA_IOCHRDY Freescale Semiconductor Pad Type V1 General IO U1 General IO U3 General IO T5 General IO T1 General IO T4 General IO T3 General IO R5 General IO T2 General IO ...

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... VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VBAT_RTC — VDD_IO — VBAT_RTC — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — Freescale Semiconductor ...

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... PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 Freescale Semiconductor Pad Type PCI (54 Total) U23 PCI F22 PCI U24 PCI V26 PCI U25 PCI R22 PCI U26 PCI T24 PCI ...

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... VDD_IO — VDD_IO 4 VDD_IO 4 VDD_IO 4 VDD_IO 4 VDD_IO 4 VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — Freescale Semiconductor ...

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... PSC5_2 PSC5_3 PSC5_4 PSC6_0 PSC6_1 PSC6_2 PSC6_3 PSC6_4 PSC7_0 PSC7_1 PSC7_2 PSC7_3 PSC7_4 PSC8_0 PSC8_1 PSC8_2 PSC8_3 PSC8_4 PSC9_0 Freescale Semiconductor Pad Type B14 General IO E13 General IO A14 General IO D13 General IO AF3 General IO AB5 General IO AC4 General IO AD4 General IO AF4 General IO ...

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... VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO — VDD_IO 6 VDD_IO 3 VDD_IO — VDD_IO 3 VDD_IO 3 VDD_IO 2, 5 VDD_IO — VDD_IO 1, 6 VDD_IO 2, 6 VDD_IO 1, 6 Oscillator Input Oscillator Output VBAT_RTC Oscillator Input VBAT_RTC Oscillator Output VBAT_RTC — Freescale Semiconductor ...

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... USB_UID USB2_VBUS_PWR_FA ULT USB2_DRVVBUS SATA PHY without Power and Ground Supplies (7 Total) SATA_XTALI SATA_XTALO SATA_ANAVIZ SATA_TXN SATA_TXP SATA_RXP SATA_RXN Freescale Semiconductor Pad Type GP Input Only (4 Total) A19 Analog Input E17 Analog Input C18 Analog Input B18 Analog Input DDR Reference Voltage ...

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... E18, F2, F3, F4, F5, F21, G5, H6, H23, L12, L13, L14, L15, L16, L21, M2, M4, M11, M12, M13, M14, M15, M16, N5, N11, N12, N13, N14, N15, N16, MPC5121E/MPC5123 Data Sheet, Rev. 3 Power Supply Notes — — — — — — — — Freescale Semiconductor ...

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... USB_RREF USB_VSSA_BIAS USB_VDDA_BIAS USB_VSSA USB_VDDA SATA_RESREF SATA_VDDA_3P3 SATA_VDDA_1P2 SATA_VDDA_VREG SATA_PLL_VDDA1P2 Freescale Semiconductor Pad Type N23, N25, P11, P12, Ground P13, P14, P15, P16, R11, R12, R13, R14, R15, R16, T6, T11, T12, T13, T14, T15, U21, V23, V25, Y24, AA6, AA10, AA11, ...

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... Max Unit SpecID −0.3 1.47 V −0.3 3.6 V −0.3 3.6 V –0.3 3.6 V −0.3 3.6 V −0.3 3.6 V −0.3 3.6 V −0.3 3.6 V −0.3 2.6 V −0.3 1.47 V −0.3 1.47 V −0.3 3.6 V Freescale Semiconductor D1.1 D1.2 D1.3 D1.4 D1.5 D1.6 D1.7 D1.8 D1.9 D1.10 D1.11 D1.12 ...

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... Input Reference Voltage (DDR/DDR2) Termination Voltage (DDR2) Supply voltage – System APLL, System Oscillator Supply voltage – e300 APLL 3 Supply voltage – RTC (Hibernation) Supply voltage – FUSE Programming Supply voltage – FUSE Reading Freescale Semiconductor Sym USB_VDDA USB_VDDA_BIAS USB_VBUS Vin Vin Vin Vinos ...

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... D2.21 VDD_MEM V D2.22 — _IO DDR VDD_MEM V D2.23 — _IO DDR2 VDD_MEM V D2.24 — _IO LPDR o — +85 C D2.25 o — +125 C D2.26 Max Unit SpecID — V D3.1 — V D3.2 — V D3.3 — V D3.4 L — V D3.5 — V D3.6 — V D3.7 Freescale Semiconductor ...

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... Output high voltage IOH is driver dependent Output high voltage IOH is driver dependent VDD_MEM_IO Output high voltage IOH is driver dependent VDD_MEM_IO Output high voltage IOH is driver dependent VDD_MEM_IO Output low voltage IOL is driver dependent Freescale Semiconductor Sym Min SV Vxtal+0.4V IH (VDD_IO/2)+0.4V UV Vxtal+0.4V IH (VDD_IO/2)+0. (VBAT_RTC/5)+0 ...

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... Fall time Current Current max (ns) Ioh (mA) Iol (mA) 1.4 1 140 183 Freescale Semiconductor Unit SpecID V D3.31 V D3.32 V D3.33 V D3.34 mA D3.35 pF D3.36 pF D3.37 Ω D3.38 SpecID 35 D3.41 D3.42 D3.43 D3.44 ...

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... V Human Body Model (HBM) – JEDEC JESD22-A114-B HBM V Machine Model (MM) – JEDEC JESD22-A115 MM V Charge Device Model (CDM) – JEDEC JESD22-C101 CDM Freescale Semiconductor Drive Select/Slew Rise time Rate Control max (ns) configuration 0 (000) configuration 1 (001) configuration 2 (010) configuration 6 (110) configuration 1 (1) ...

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... Table 9. Power Dissipation Core Power Supply (VDD_CORE) High-Performance e300 = 300 MHz, CSB = 200 MHz 1, 800 300 PHY Power Supplies (USB_VDDA, SATA_VDDA) 200 NOTE MPC5121E/MPC5123 Data Sheet, Rev × PPHYs SpecID Unit mW D5.1 mW D5.2 uW D5.3 mW D5.4 mW D5.5 mW D5.6 Freescale Semiconductor Eqn. 1 Eqn. 2 ...

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... Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: Freescale Semiconductor Table 10. Thermal Resistance Data Board Layers ...

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... The USB PHY contains its own oscillator with the input USB_XTALI and an embedded PLL. The SATA PHY contains its own oscillator with the input SATA_XTALI and an embedded PLL θ θ θ Ψ × MPC5121E/MPC5123 Data Sheet, Rev. 3 Eqn. 4 Eqn. 5 Freescale Semiconductor ...

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... SYS_XTALI duty cycle is measured at V 3.2.2 RTC Oscillator Electrical Characteristics Table 13. RTC Oscillator Electrical Characteristics Characteristic RTC_XTALI frequency 3.2.3 System PLL Electrical Characteristics Characteristic Sys PLL input clock frequency 2 Sys PLL input clock jitter Freescale Semiconductor Sym Min f 15.6 sys_xtal t CYCLE t t DUTY DUTY ...

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... O3.4 — O3.5 μs — 200 O3.6 μs — 170 O3.7 Typical Max Unit SpecID — 400 MHz O4.1 — 800 MHz O4.3 — 200 MHz O4.4 — O4.5 μs — 200 O4.6 and f (f core VCOcore core Freescale Semiconductor = ...

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... Output Loading: All Outputs 3.3.2 AC Operating Frequency Data Table 16 provides the operating frequency information for the MPC5121e/MPC5123. e300 Processor Core SDRAM Clock CSB Bus Clock IP Bus Clock PCI Clock LPC Clock Freescale Semiconductor • SDHC • DIU • SPDIF • CAN 2 • • ...

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... Table 17. Reset Rise / Fall Timing Min Max — 1 — 1 — 1 — 1 — 1 — 1 MPC5121E/MPC5123 Data Sheet, Rev. 3 Max Units SpecID 83 MHz A1.7 100 MHz A1.8 66.6 MHz A1.9 100 MHz A1.10 Unit SpecID ms A3.4 ms A3.5 ms A3.6 ms A3.7 ms A3.8 ms A3.9 Freescale Semiconductor ...

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... SYS_XTALI PORESET HRESET SRESET t S_POR_CONF RST_CONF[31:0] ADDR[31:0] SYS_XTALI PORESET HRESET SRESET RST_CONF[31:0] ADDR[31:0] Freescale Semiconductor t HRVAL t SRVAL t EXEC t H_POR_CONF Figure 3. Power-Up Behavior t PORHold t HRVAL t S_POR_CONF t H_POR_CONF Figure 4. Power-On Reset Behavior MPC5121E/MPC5123 Data Sheet, Rev. 3 Electrical and Thermal Characteristics t SRVAL t EXEC 29 ...

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... RST_CONF Figure 5. HRESET Behavior t SRHOLD no new fetch of the RST_CONF Figure 6. SRESET Behavior Table 18. Reset Timing Description MPC5121E/MPC5123 Data Sheet, Rev SRVAL t EXEC t SRMIN t EXEC Value SYS_XTALI 4 cycles 26810 cycles 32 cycles 4 cycles Freescale Semiconductor SpecID A3.10 A3.11 A3.12 A3.13 ...

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... The MPC5121e/MPC5123 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory device. This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the DC Electrical Characteristics. Freescale Semiconductor Table 18. Reset Timing (continued) Description Symbol t PICWID MPC5121E/MPC5123 Data Sheet, Rev ...

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... MPC5121E/MPC5123 Data Sheet, Rev. 3 Max Unit Notes — 0.1 0.53 t 1,3 CK 0.53 t 1,3 CK 0.25 t 2,3 CK — ps 2,3 — ps 2,3 — ps 2,3 — 600 TBD ps 1,2,3,4,5 window position is shifted accordingly. Freescale Semiconductor SpecID A5.1 A5.2 A5.3 A5.4 A5.5 A5.6 A5.7 A5.8 A5.9 A5.10 A5.11 ...

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... DQ, DM(out) Figure and Figure 9 shows the DDR SDRAM read timing DQS(in) Any DQ(in) MCK Command Address DQS(in) Figure 10 provides the AC test load for the DDR bus. Freescale Semiconductor t DQSS Figure 7. DDR Write Timing t DQSQ t DQSQ Figure 8. DDR Read Timing DQS Read ...

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... Figure 11. PCI CLK Waveform Table 21. PCI CLK Specifications 1 66 MHz 2 Min Max 1 — 6 — 2 1.5 4 MPC5121E/MPC5123 Data Sheet, Rev. 3 VDD_MEM_IO Ω Table 21 0.4Vcc, p-to-p (minimum) 33 MHz Units SpecID Min Max 30 — ns A6.1 11 — ns A6.2 11 — V/ns A6.4 Figure 11. Freescale Semiconductor summarizes ...

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... Definition of Acronyms and Terms Wait State DC = Dead Cycle HC = Hold Cycle DS = Data Size in Bytes BBT = Burst Bytes per Transfer AL = Address latch enable Length ALT = Chip select/Address Latch Timing t = LPC clock period LPCck Freescale Semiconductor Table 22. PCI Timing Parameters 66 MHz 2 Min Max 2 6 1,2 ...

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... LPCck OD AL*2*t ns LPCck AL*t ns LPCck t ns LPCck ns — ns — (ALT*(AL*2)+2+WS)*t ns LPCck Freescale Semiconductor A7.1 A7.2 A7.3 A7.4 A7.5 A7.6 A7.7 A7.8 A7.9 A7.10 A7.11 A7.12 A7.13 A7.14 A7.15 A7.16 A7.17 A7.18 A7.19 A7.20 A7.21 A7.22 A7.23 ...

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... DATA (rd) ACK TS TSIZ[1:0] Figure 12. Timing Diagram – Non-MUXed non-Burst Mode ACK is asynchonous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. Freescale Semiconductor Table 23. LPC Timing (continued) Min (ALT*(AL*2)+2+WS +BBT/DS)*t LPCck (ALT*(AL*2)+2.5+WS +BBT/DS)*t ...

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... DATA (rd) ACK Figure 13. Timing Diagram – Non-MUXed Synchronous Read Burst Mode 3.3.7.1.3 Non-Muxed Synchronous Write Burst Mode LPC_CLK CS[x] t ADDR TS R/W DATA (wr) ACK Figure 14. Timing Diagram – Non-MUXed Synchronous Write Burst Valid Address Valid Address MPC5121E/MPC5123 Data Sheet, Rev Freescale Semiconductor ...

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... TS OE R/W DATA (rd) ACK Figure 15. Timing Diagram – Non-MUXed Asynchronous Read Burst 3.3.7.1.5 Non-MUXed Aynchronous Write Burst Mode LPC_CLK CS[x] ADDR[31:n+1] ADDR[n:0] TS R/W DATA (wr) ACK Figure 16. Timing Diagram – Non-MUXed Aynchronous Write Burst Freescale Semiconductor Valid Address (Page address) Valid Address ...

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... AD[31:0] (wr) AD[31:0] (rd) R/W ALE TS CS[x] OE ACK TSIZ[1:0] Figure 17. Timing Diagram – MUXed non-Burst Mode ACK is asynchonous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted Address Address NOTE MPC5121E/MPC5123 Data Sheet, Rev. 3 Valid Write Data Freescale Semiconductor ...

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... LPC_CLK AD[31:0] (rd) t ALE TS CSx OE R/W ACK Figure 18. Timing Diagram – MUXed Synchronous Read Burst 3.3.7.2.3 MUXed Synchronous Write Burst Mode LPC_CLK AD[31:0] (wr) t ALE TS CSx R/W ACK Figure 19. Timing Diagram – MUXed Synchronous Write Burst Freescale Semiconductor t 17 Address Address MPC5121E/MPC5123 Data Sheet, Rev ...

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... NFC_CE[1:0] NFC_WE NFC_ALE NFIO[7:0] 42 tCLS tCS tWP tALS tALH tDS tDH command Figure 20. Command Latch Cycle Timing tCLS tCS tCH tWC tWH tWP tALH tALS tDS tDH Address Figure 21. Address Latch Cycle Timing MPC5121E/MPC5123 Data Sheet, Rev. 3 tCLH tCH Freescale Semiconductor ...

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... NFC_ALE NFIO[15:0] R/B Timing parameter tCLS NFC_CLE setup Time tCLH NFC_CLE Hold Time tCS NFC_CE[1:0] Setup Time tCH NFC_CE[1:0] Hold Time Freescale Semiconductor tCLS tCS tWC tWH tWP tDS tDH Data to NF Figure 22. Write Data Latch Timing tRC tREH tRP tREA ...

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... T-1 T-1 T-1 T-2 T-1 2T T-1 5T+2 1.5T-1 2T 0.5T MPC5121E/MPC5123 Data Sheet, Rev. 3 Max. value Unit SpecID — ns A8.5 — ns A8.6 — ns A8.7 — ns A8.8 — ns A8.9 — ns A8.10 — ns A8.11 — ns A8.12 — ns A8.13 — ns A8.14 — ns A8.15 Freescale Semiconductor ...

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... Max buffer propagation delay tcable1 Cable propagation delay for ata_data tcable2 Cable propagation delay for control signals: ATA_DIOR, ATA_DIOW, ATA_IORDY, ATA_DMACK Freescale Semiconductor NOTE Table 3-25. PATA Timing Parameters Meaning MPC5121E/MPC5123 Data Sheet, Rev. 3 Electrical and Thermal Characteristics Table 3-25 specify the ATA timing ...

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... Value Cable Cable Cable t2r trd1 must be observed. How to meet calculate and programming time_1, see Reference Manual calculate and programming time_2r, see Reference Manual calculate and programming time_9, see Reference Manual Freescale Semiconductor SpecID A9.14 A9.15 A9.16 SpecID A9.20 A9.21 A9.22 ...

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... In PIO write mode, timing waveforms are somewhat different as shown in ADDR DIOR DIOW buffer_en Write Data (15:0) IORDY IORDY To fulfill this timing, several parameters need to be observed as shown in Freescale Semiconductor Value Figure t1 t2r ton tA Figure 25. PIO Write Mode Timing Table MPC5121E/MPC5123 Data Sheet, Rev. 3 ...

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... A9.31 time_2w, see Reference Manual time_9, see Reference A9.32 Manual If not met, increase time_2w A9.33 calculate and programming A9.34 time_4, see Reference Manual calculate and programming A9.35 time_ax, see Reference Manual time_1, time_2r, time_9 A9.36 A9.37 — A9.38 — Freescale Semiconductor ...

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... Timing in multiword DMA mode is given in DMARQ ADDR DMACK DIOR Read Data (15:0) DMARQ ADDR DMACK buffer_en DIOW Write Data (15:0) To meet this timing, a number of timing parameters must be controlled as shown in Freescale Semiconductor Figure 26 and Figure tgr tfr Figure 26. MDMA Read Timing tm ton td1 ...

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... Reference Manual calculate and A9.42 programming time_k, see Reference Manual time_d, time_k A9.43 time_d, see A9.44 Reference Manual — A9.45 time_d A9.46 time_k A9.47 time_d, time_k A9.48 calculate and A9.49 programming time_jn, see Reference Manual — A9.50 Freescale Semiconductor ...

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... ADDR DMARQ DMACK DIOR DIOW IORDY Data Read Figure 28. UDMA In Transfer Start Timing Diagram Freescale Semiconductor tack tenv tds MPC5121E/MPC5123 Data Sheet, Rev. 3 Electrical and Thermal Characteristics tc1 tc1 tdh 51 ...

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... Figure 29. UDMA In Host Terminates Transfer tc1 tc1 tss1 tli5 tds tdh Table 29. MPC5121E/MPC5123 Data Sheet, Rev. 3 tack tmli tmli tzah tzah ton tdzfs tcvh toff tack tmli tmli tzah tzah ton tdzfs tcvh toff Freescale Semiconductor ...

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... UDMA out transfer start • Figure 32 gives timing for host terminating UDMA out transfer • Figure 33 gives timing for device terminating UDMA out transfer. Freescale Semiconductor Table 29. Timing Parameters UDMA in Burst Value MPC5121E/MPC5123 Data Sheet, Rev. 3 Electrical and Thermal Characteristics How to Meet SpecID calculate and A9 ...

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... Figure 31. UDMA Out Transfer Start Timing Diagram ADDR DMARQ DMACK DIOW DIOR Data Write IORDY buffer_en Figure 32. UDMA Out Host Terminates Transfer 54 tenv ton tdzfs tdvs tdvh tli1 tss tcyc tli2 tcyc1 tdzfs_mli tli3 MPC5121E/MPC5123 Data Sheet, Rev. 3 tcyc tcyc tdvs trfs1 tack tcvh toff Freescale Semiconductor ...

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... Freescale Semiconductor tli2 tcyc Table 30. Table 30. Timing Parameters UDMA Out Burst Value tack(min) = (time_ack * T) – (tskew1 + tskew2) tenv(min) = (time_env * T) – (tskew1 + tskew2) tenv(max) = (time_env * T) + (tskew1 + tskew2) tdvs = (time_dvs * T) – (tskew1 + tskew2) tdvs = (time_dvh * T) – ...

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... A9.71 programming time_ss, see Reference Manual A9.72 — — A9.73 — A9.74 — A9.75 calculate and A9.76 programming time_cvh, see Reference Manual A9.77 — Max Unit SpecID — ns A11.1 — ns A11.2 1 65% RX_CLK Period A11.3 1 65% RX_CLK Period A11.4 Freescale Semiconductor ...

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... TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 Specification. TX_CLK (Input) TXD[3:0] (Outputs) TX_EN TX_ER Figure 35. Ethernet Timing Diagra – MII Tx Signal Sym Description t CRS, COL minimum pulse width 9 Figure 36. Ethernet Timing Diagram – MII Async Freescale Semiconductor Table 32. MII Tx Signal Timing Min 3 — 35% 35% ...

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... This section specifies the USB ULPI timing. For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004. 58 Min 10 1 160 160 400 MPC5121E/MPC5123 Data Sheet, Rev. 3 Max Unit — — ns — ns — ns — Freescale Semiconductor SpecID A11.10 A11.11 A11.12 A11.13 A11.14 A11.15 ...

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... DD 3.3.13 On-Chip USB PHY The USB PHY is an USB2.0 compatible PHY integrated on-chip. See Chapter 7 in the USB Specification Rev. 2.0 at www.usb.org. 3.3.14 SDHC Figure 39 depicts the timings of the SDHC. Freescale Semiconductor Figure 38. ULPI Timing Diagram Table 35. Timing Specifications – ULPI ...

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... IH MPC5121E/MPC5123 Data Sheet, Rev. 3 SD1 SD7 SD8 Min Max Unit 0 400 kHz 0 25/50 MHz 0 20/52 MHz 100 400 kHz 10/7 ns 10/7 ns 10 TH+3 ns 2.5 ns 2.5 ns Freescale Semiconductor SpecID A14.1 A14.2 A14.3 A14.4 A14.5 A14.6 A14.7 A14.8 A14.9 A14.10 A14.11 ...

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... DIU_DE signal. You can select the polarity of the DIU_HSYNC and DIU_VSYNC signal via the SYN_POL register, whether active-high or active-low, the default is active-high. The DIU_DE signal is always active-high. And, pixel clock inversion and a flexible programmable pixel clock delay is also supported, programed via the DIU Clock Config Register (DCCR) in the system clock module. Freescale Semiconductor LINE 3 LINE MPC5121E/MPC5123 Data Sheet, Rev ...

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... Display Pixel Clock Period PCP t HSYNC Pulse Width PWH t HSYNC Back Porch Width BPH 62 t HSP t BPH VSP t BPV Value 1 15 PW_H * t PCP BP_H * t PCP MPC5121E/MPC5123 Data Sheet, Rev FPH DELTA_X Invalid Data FPV Invalid Data DELTA_Y Unit Freescale Semiconductor SpecID A15.1 A15.2 A15.3 ...

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... LCD Interface Data Setup Time DSU t LCD Interface Data Hold Time DHD t LCD Interface Control Signal Setup Time CSU t LCD Interface Control Signal Hold Time CHD Freescale Semiconductor Value FP_H * t PCP DELTA_X * t PCP (PW_H + BP_H + DELTA_X + FP_H PW_V * t HSP BP_V * t HSP ...

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... IP-Bus Cycle — 7 — IP-Bus Cycle 2 2 — IP-Bus Cycle 2 20 — IP-Bus Cycle 2 10 — IP-Bus Cycle 2 C interface is Freescale Semiconductor SpecID A18.1 A18.2 A18.3 A18.4 A18.5 A18.6 A18.7 SpecID A18.8 A18.9 A18.10 A18.11 A18.12 A18.13 A18.14 A18.15 A18.16 ...

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... FrameSync valid after clock edge 6 FrameSync invalid after clock edge 7 Output Data valid after clock edge 8 Input Data setup time 1 Bit Clock cycle time Freescale Semiconductor NOTE Output timing is specified at a nominal 50 pF load Figure 44. Timing Diagram – Input/Output 2 S Mode ...

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... Output timing is specified at a nominal 50 pF load. MPC5121E/MPC5123 Data Sheet, Rev Master Mode 2 S Slave Mode Min Typ Max Units 40.0 — — — 50 — % 1.0 — — ns — — 14.0 ns 1.0 — — ns 1.0 — — ns Freescale Semiconductor SpecID A20.9 A20.10 A20.11 A20.12 A20.13 A20.14 ...

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... Clock pulse high time 3 Clock pulse low time 4 FrameSync valid after rising clock edge 5 Output Data valid after rising clock edge 6 Input Data setup time 7 Input Data hold time Freescale Semiconductor Table 43. Timing Specifications – AC97 Mode Description NOTE Output timing is specified at a nominal 50 pF load. ...

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... MPC5121E/MPC5123 Data Sheet, Rev. 3 Min Max Units SpecID 30.0 — ns A20.26 15.0 — ns A20.27 30.0 — ns A20.28 — 8.9 ns A20.29 — 8.9 ns A20.30 6.0 — ns A20.31 1.0 — ns A20.32 — TSCK ns A20.33 15.0 — ns A20.34 — 7.9 ns A20.35 — 7.9 ns A20.36 Freescale Semiconductor ...

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... Slave select clock delay 4 Input Data setup time 5 Input Data hold time 6 Output data valid after SS 7 Output data valid after SCK 8 Slave disable lag time 9 Minimum Sequential Transfer delay = Bus clock cycle time Freescale Semiconductor Description NOTE Output timing is specified at a nominal 50 pF load. ...

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... Output timing is specified at a nominal 50 pF load. MPC5121E/MPC5123 Data Sheet, Rev Min Max Units SpecID 30.0 — ns A20.46 15.0 — ns A20.47 30.0 — ns A20.48 — 8.9 ns A20.49 6.0 — ns A20.50 1.0 — ns A20.51 — TSCK ns A20.52 15.0 ns A20.53 — — 7.9 ns A20.54 — 7.9 ns A20.55 Freescale Semiconductor ...

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... SCK pulse width, 50% SCK duty cycle 3 Slave select clock delay 4 Output data valid 5 Input Data setup time 6 Input Data hold time 7 Slave disable lag time 8 Minimum Sequential Transfer delay = 2 * IP-Bus clock cycle time Freescale Semiconductor Description NOTE Output timing is specified at a nominal 50 pF load. ...

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... Program current to program one fuse bit FUSEWR 1 The program length is defined by the value defined in the EPM_PGM_LENGTH bits of the IIM module Description Table 49. Fusebox Characteristics Description MPC5121E/MPC5123 Data Sheet, Rev Min Unit SpecID A21.1 Min Max Units SpecID 125 — us A22.1 — A22.2 Freescale Semiconductor ...

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... TRST is an asynchronous signal. The setup time is for test purposes only. 2 Non-test, other than TDI and TMS, signal input timing with respect to TCK. 3 Non-test, other than TDO, signal output timing with respect to TCK. TCK Figure 52. Timing Diagram – JTAG Clock Input Freescale Semiconductor Table 50. JTAG Timing Specification Characteristic ...

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... Numbers shown reference JTAG Timing Specification Table Figure 53. Timing Diagram – JTAG TRST 8 9 Numbers shown reference JTAG Timing Specification Table 12 Output Data Valid 13 Numbers shown reference JTAG Timing Specification Table MPC5121E/MPC5123 Data Sheet, Rev Input Data Valid Output Data Valid 10 11 Input Data Valid Freescale Semiconductor ...

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... Each of the independent PLL power supplies require filtering external to the device. The following drawing recommendation for the required filter circuit. Each circuit should be placed as close as possible to the specific AV nearby circuits. All traces should be as low impedance as possible, especially ground pins to the ground plane. Freescale Semiconductor Table 51 lists the timing parameters. f PIX_CLK ...

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... Figure 58. Recommended Connection for Pins of Unused SATA PHY 76 R1=10 Ω C1=1 μF C2=0.1 μF Figure 57. Power Supply Filtering MPC5121e/MPC5123 SATA_XTALI SATA_XTALO SATA_ANAVIZ SATA_RESREF SATA_TXP SATA_TXN SATA_RXP SATA_RXN SATA_VDDA_3P3 SATA_VDDA_1P2 SATA_VDDA_VREG SATA_PLL_VDDA1P2 SATA_PLL_VSSA SATA_RX_VSSA SATA_TX_VSSA MPC5121E/MPC5123 Data Sheet, Rev. 3 AVDD device pin Freescale Semiconductor ...

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... Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset performance, the TRST signal must be asserted during power-on reset. Freescale Semiconductor MPC5121e/MPC5123 USB_XTALI ...

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... There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector. 4.5.2.1 Boards Interfacing the JTAG Port via a COP Connector The MPC5121e/MPC5123 functional pin interface and internal logic provides access to the embedded e300 processor core through the Freescale standard COP/BDM interface. reflects only the COP/BDM connector order. BDM MPC5121e/MPC51 ...

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... TRST and PORESET is not recommended. To reset the MPC5121e/MPC5123 via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5121e/MPC5123. The circuitry shown in any other board sources can drive PORESET. Freescale Semiconductor Internal BDM Connector Pull Up/Down ...

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... TDI 3 10Kohm CKSTP_OUT 15 10Kohm CKSTP_IN 8 halted ( qack ( Figure 61. COP Connector Diagram MPC5121E/MPC5123 Data Sheet, Rev. 3 PORESET HRESET VDD_IO VDD_IO SRESET VDD_IO TRST VDD_IO TMS VDD_IO TCK TDO VDD_IO TDI VDD_IO CKSTP_OUT VDD_IO CKSTP_IN (LPC_CLK) Figure 62 shows the connection Freescale Semiconductor ...

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... SRESET Figure 62. TRST Wiring for Boards without COP Connector 5 Package Information This section details package parameters and dimensions. The MPC5121e/MPC5123 is available in a Thermally Enhanced Plastic Ball Grid Array (TEPBGA), see information on the TEPBGA. Freescale Semiconductor PORESET HRESET 10 Kohm VDD_IO 10 Kohm VDD_IO ...

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... Package Information 5.1 Package Parameters Package outline Interconnects Module height (typical) Solder Balls Ball diameter (typical) 5.2 Mechanical Dimensions 82 Table 53. TEPBGA Paramaters 27 mm Pitch 1.00 mm 2.25 mm 96.5 Sn/3.5Ag (VY package) 0.6 mm MPC5121E/MPC5123 Data Sheet, Rev. 3 × 516 Freescale Semiconductor ...

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... MDQ6 VDD_ VDD_I VDD_I PSC5_ AE MDQ2 MEM_I MDQ7 VSS VDD_I PSC3_ PSC3_ AF MDQ0 MDQ3 MDQ4 Figure 63. Ball Map for the MPC5121e 516-PBGA Package Freescale Semiconductor PSC7_ PSC6_ PSC6_ PSC6_ PSC11 PSC10 PSC2_ PSC1_ PSC7_ PSC6_ VDD_I PSC11 PSC10 PSC2_ VDD_I VSS ...

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... Figure 64. Mechanical Dimension and Bottom Surface Nomenclature of the MPC5121e/MPC5123 TEPBGA 1 All dimensions are in millimeters. 2 Dimensions and tolerances per ASME Y14.5M-1994. 3 Maximum solder ball diameter measured parallel to datum A. 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 84 MPC5121E/MPC5123 Data Sheet, Rev. 3 Freescale Semiconductor ...

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... Product Documentation This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com. Table 54 provides a revision history for this document. Revision Rev. 0, DraftA Rev. 0, DraftB Rev. 0, DraftC Rev. 1 Rev. 2 Rev. 3 Freescale Semiconductor Table 54 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...