SPC5121YVY400BR Freescale, SPC5121YVY400BR Datasheet - Page 31

• Manufacturer Part Number: SPC5121YVY400BR
• Manufacturer: Freescale

Specifications of SPC5121YVY400BR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.3.4
The MPC5121e/MPC5123 provides three different kinds of external interrupts:
IPIC inputs must be valid for at least tPICWID to ensure proper operation in edge triggered mode.
3.3.5
The MPC5121e/MPC5123 memory controller supports three types of DDR devices:
JEDEC standards define the minimum set of requirements for complient memory devices:
The MPC5121e/MPC5123 supports the configuration of two output drive strengths for DDR2 and LPDDR:
The MPC5121e/MPC5123 memory controller supports dynamic on-die termination in the host device and in the DDR2 memory
device.
This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the DC Electrical
Characteristics.
Freescale Semiconductor
t
t
t
HR_SR_DELAY
H_POR_CONF
S_POR_CONF
•
•
•
•
•
•
•
•
t
Symbol
t
HRHOLD
SRHOLD
t
SRMIN
IRQ interrupts
GPIO interrupts with simple interrupt capability (not available in power-down mode)
WakeUp interrupts
DDR-1 (SSTL_2 class II interface)
DDR-2 (SSTL_18 interface)
LPDDR/Mobile-DDR (1.8V I/O supply voltage)
— JEDEC STANDARD, DDR2 SDRAM SPECIFICATION, JESD79-2C, MAY 2006
— JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification, JESD79E, May 2005
— JEDEC STANDARD, Low Power Double Data Rate (LPDDR) SDRAM Specification, JESD79-4, May 2006
full drive strength
half drive strengh (intended for ligther loads or point-to-point environments)
SDRAM (DDR)
External Interrupts
1
IPIC inputs - minimum pulse witdh
T is the IP bus clock cycle. T= 12 ns is the minimum value (for the maximum IP bus freqency
of 83 MHz).
Reset configuration setup time before assertion of PORESET
Reset configuration hold time after assertion of PORESET
Time from falling edge of HRESET to falling edge of SRESET
Time HRESET must be held low before a qualified reset occurs
Time SRESET must be held low before a qualified reset occurs
Time SRESET is asserted after it has been qualified
Description
Table 19. IPIC Input AC Timing Specifications
MPC5121E/MPC5123 Data Sheet, Rev. 3
Table 18. Reset Timing (continued)
Description
Symbol
t
PICWID
Min
2T
Electrical and Thermal Characteristics
1
Unit
ns
SYS_XTALI
SpecID
4 cycles
4 cycles
4 cycles
1 cycles
A4.1
1 cycle
1 cycle
Value
SpecID
A3.14
A3.15
A3.16
A3.17
A3.18
A3.19
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