SPC5121YVY400BR Freescale, SPC5121YVY400BR Datasheet - Page 44

• Manufacturer Part Number: SPC5121YVY400BR
• Manufacturer: Freescale

Specifications of SPC5121YVY400BR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Electrical and Thermal Characteristics
T is the flash clock cycle.
T= 45 ns, frequency = 22 MHz (boot configuration, IP bus = 66 MHz)
T= 36 ns, frequency = 27 MHz (maximum configurable frequency, IP bus = 83 MHz)
3.3.9
The MPC5121e/MPC5123 ATA Controller (PATA) is completely software programmable. It can be programmed to operate
with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is
completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units
(nanoseconds).
ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data
setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the
ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and
ATA drive for different ATA protocols and their respective timing. See the MPC5121e/MPC5123 Reference Manual.
The MPC5121e/MPC5123 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE
strobe in PIO and Multiword DMA modes.
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers.
This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate
with the drive.
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Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that
required by the ATA-4 specification.
Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that
required by the ATA-4 specification.
parameter
Timing
tREH
tALH
PATA
tALS
tWP
tWC
tWH
tDH
tRR
tRC
tDS
tRP
NFC_WP Pulse Width
NFC_ALE Setup Time
NFC_ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
NFC_WE Hold Time
Ready to NFC_RE Low
NFC_RE Pulse Width
READ Cycle Time
NFC_RE High Hold Time
Table 24. NFC Timing Characteristics (continued)
Description
MPC5121E/MPC5123 Data Sheet, Rev. 3
Min. value
1.5T-1
5T+2
0.5T
T-1
T-1
T-1
T-2
T-1
T-1
2T
2T
Max. value
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—
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Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SpecID
A8.10
A8.11
A8.12
A8.13
A8.14
A8.15
A8.5
A8.6
A8.7
A8.8
A8.9