MT48H8M16LFB4-75:J TR Micron Technology Inc, MT48H8M16LFB4-75:J TR Datasheet - Page 51

• Manufacturer Part Number: MT48H8M16LFB4-75:J TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75:J TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

WRITEs
Figure 27:
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN
WRITE Burst
Notes:
WRITE bursts are initiated with a WRITE command, as shown in Figure 11 on page 28.
The starting column and bank addresses are provided with the WRITE command and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element is registered coincident with the
WRITE command. Subsequent data elements are registered on each successive positive
clock edge. Upon completion of a fixed-length burst, assuming no other commands
have been initiated, the DQ will remain at High-Z and any additional input data will be
ignored (see Figure 27). A continuous page burst continues until terminated; at the end
of the page, it wraps to column 0 and continues.
Data for any WRITE burst can be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst can be followed immediately by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command (seeFigure 28 on page 52). Data n + 1 is either the last of a burst of two
or the last desired data element of a longer burst. Mobile SDRAM uses a pipelined archi-
tecture and therefore does not require the 2n rule associated with a prefetch architec-
ture. A WRITE command can be initiated on any clock cycle following a previous WRITE
command. Full-speed random write accesses within a page can be performed to the
same bank, as shown in Figure 29 on page 53, or each subsequent WRITE can be
performed to a different bank.
1. BL = 2. DQM is LOW.
Command
Address
CLK
DQ
WRITE
Bank,
Col n
T0
Din
n
Transitioning data
NOP
n + 1
T1
Din
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
51
NOP
T2
Don’t Care
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
NOP
©2008 Micron Technology, Inc. All rights reserved.
Timing Diagrams