MT48H8M16LFB4-75:J TR Micron Technology Inc, MT48H8M16LFB4-75:J TR Datasheet - Page 25

• Manufacturer Part Number: MT48H8M16LFB4-75:J TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75:J TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Commands
Table 15:
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (select bank and column, and start READ burst)
WRITE (select bank and column, and start WRITE burst)
BURST TERMINATE or deep power-down
(enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (enter self refresh mode)
LOAD MODE REGISTER
Write enable/output enable
Write inhibit/output High-Z
Truth Table – Commands and DQM Operation
Note 1 applies to all commands; notes appear below table
Notes:
10. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
Table 15 provides a quick reference of available commands. A written description of
each command follows the table. Three additional Truth Tables appear on pages 30–34;
these tables provide current state/next state information.
1. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.
2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1
3. A[0:i] provide column address (where i = the most significant column address for a given
4. This command is BURST TERMINATE when CKE is HIGH and DEEP POWER-DOWN when CKE
5. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command
6. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks precharged
7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8. Internal refresh counter controls row addressing; all inputs and I/Os are
9. A[11:0] define the op-code written to the mode register.
determine which bank is made active.
device configuration). A10 HIGH enables the auto precharge feature (non-persistent), while
A10 LOW disables the auto precharge feature. BA0 and BA1 determine which bank is being
read from or written to.
is LOW.
could coincide with data on the bus. However, the DQ column reads a
illustrate that the BURST TERMINATE command can occur when there is no data present.
and BA0, BA1 are
for CKE.
delay).
“
Don’t Care.”
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
25
CS#
H
X
X
L
L
L
L
L
L
L
L
RAS# CAS# WE#
H
H
H
H
X
X
X
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
X
X
L
L
L
L
X
H
H
H
H
X
X
L
L
L
L
DQM
L/H
L/H
X
X
X
X
X
X
X
H
L
©2008 Micron Technology, Inc. All rights reserved.
Bank/row
Bank/col
Bank/col
Op-code
ADDR
Code
X
X
X
X
X
X
“
Don’t Care” state to
“
Don’t Care” except
Commands
High-Z
Active
Valid
DQ
X
X
X
X
X
X
X
X
Notes
4, 5
7, 8
10
10
2
3
3
6
9