MT48H8M16LFB4-75:J TR Micron Technology Inc, MT48H8M16LFB4-75:J TR Datasheet - Page 40

• Manufacturer Part Number: MT48H8M16LFB4-75:J TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75:J TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Figure 16:
Temperature-Compensated Self Refresh (TCSR)
Partial-Array Self Refresh (PASR)
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN
En + 2
0
0
1
1
En + 1
Extended Mode Register
0
1
0
1
En
0
–
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
...
Notes:
0
–
E10
0
–
E9
0
–
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
The EMR must be programmed with E[n:7] set to “0.” It must be loaded when all banks
are idle and no bursts are in progress, and the controller must wait the specified time
before initiating any subsequent operation. Violating either of these requirements
results in unspecified operation. After the values are entered, the EMR settings are
retained even after exiting deep power-down mode.
Mobile SDRAM includes a temperature sensor that is implemented for automatic
control of the self refresh oscillator on the device. Programming the TCSR bits has no
effect on the device. The self refresh oscillator will continue refresh at the optimal
factory-programmed rate for the device temperature.
For further power savings during self refresh, the PASR feature enables the controller to
select the amount of memory to be refreshed during self refresh. The refresh options are:
• Full array: banks 0, 1, 2, and 3
• One-half array: banks 0 and 1
• One-quarter array: bank 0
• One-eighth array: bank 0 with row address most significant bit (MSB) = 0
• One-sixteenth array: bank 0 with row address MSB = 0 and row address MSB - 1 = 0
n+2
1
BA1
E8
0
–
n+1
0
BA0
E7–E0
Valid
–
A
n
...
Operation
Normal operation
All other states reserved
...
10
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E7
0
0
0
0
1
1
1
1
E6
0
0
1
1
0
0
1
1
9
E5
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
0
1
0
1
0
1
0
1
8
40
7
DS
6
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
E2
0
0
0
0
1
1
1
1
TCSR
4
E1
0
0
1
1
0
0
1
1
1
3
E0
0
1
0
1
0
1
0
1
2
PASR
Partial-Array Self Refresh Coverage
Full array
1/2 array
1/4 array
Reserved
Reserved
1/8 array
1/16 array
Reserved
1
0
©2008 Micron Technology, Inc. All rights reserved.
Register Definition
Address bus
Extended mode
register (Ex)