MT48H8M16LFB4-75:J TR Micron Technology Inc, MT48H8M16LFB4-75:J TR Datasheet - Page 24

• Manufacturer Part Number: MT48H8M16LFB4-75:J TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75:J TR

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Functional Description
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN
Mobile SDRAM devices are quad-bank DRAM that operate at 1.8V and include a
synchronous interface. All signals are registered on the positive edge of the clock signal,
CLK.
Read and write accesses to SDRAM are burst oriented; accesses start at a selected loca-
tion and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command, that is followed by a READ
or WRITE command. The address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0 and BA1 select the bank). The
address bits registered coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
Mobile SDRAM provides for programmable READ or WRITE burst lengths. An auto
precharge function may be enabled to provide a self-timed row precharge that is initi-
ated at the end of the burst sequence.
Mobile SDRAM uses an internal pipelined architecture to achieve high-speed operation.
This architecture enables changing the column address on every clock cycle to achieve a
high-speed, fully random access. Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide seamless high-speed, random-
access operation.
Mobile SDRAM is designed to operate in 1.8V memory systems. An auto refresh mode is
provided, along with power-saving, power-down, and deep power-down modes. All
inputs and outputs are LVTTL-compatible.
Mobile SDRAM offers substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between internal banks in order to hide
precharge time, and the capability to randomly change column addresses on each clock
cycle during a burst access.
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Functional Description
©2008 Micron Technology, Inc. All rights reserved.