PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 65

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.3.5
The upstream D-channel is arbitrated between the S-bus, the internal HDLC controller
and external HDLC controllers via the TIC bus (S/G, BAC, TBA bits) according to the
IOM
to set the priority (8 or 10) of all HDLC-controllers connected to IOM
particularly useful for use of the T-SMINT
2.3.5.1
Figure 26
the microcontroller.
•
Figure 26
2.3.5.2
The TIC bus is implemented to organize the access to the C/I0-channel and to the D-
channel from up to 7 D-channels HDLC controllers. The arbitration mechanism must be
activated by setting MODEH.DIM2-0=00x.
The arbitration mechanism is implemented in the last octet in IOM
IOM
generated by software (µC access to the C/I0-channel via CIX0 register) or by an internal
1)
Data Sheet
The A/B-bit is not supported by the U-transceiver
â
â
D
-2 Reference Guide
-2 interface (see
E-Bit
shows a scenario for the local D-channel arbitration between the S-bus and
D-Channel Access Control
Application Example for D-Channel Access Control
TIC Bus Handling
Bus
D-Channel Arbitration: C has no HDLC and no Direct Access to TIC
T-SMINT
S
Figure
Arbitr.
1)
IOM-2 i/f
Prio
IOM-2
. Further to the implementation in the INTC-Q it is possible,
â
IX
27). An access request to the TIC bus may either be
BAC, TBA
S/G
HDLC
µP - i/f
e.g. C513,
C161-RI
µC
â
51
CIX0
CIR0
IX together with the UTAH.
U
µC writes data into FIFO,
transmission happens automatically
Q-SMINTIX delivers an interrupt,
when transmission is complete
Functional Description
D
â
-2 channel 2 of the
.
â
PEF 81902
-2, which is
2001-11-12