PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 176

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.4.20
CIR1
Value after reset: FE
CODR1
CICW
CI1E
4.4.21
CIX1
Value after reset: FE
Data Sheet
7
0 =
1 =
Note: Access is always granted by default to the T-SMINT
CIR1 - Command/Indication Receive 1
C/I1-Code Receive
C/I-Channel Width
Contains the read back value from CIX1 register (see below)
0 =
1 =
C/I1-channel Interrupt Enable
Contains the read back value from CIX1 register (see below)
0 =
1 =
CIX1 - Command/Indication Transmit 1
Address (TBA2-0, CIX0 register) ‘7’, which has the lowest priority in a
bus configuration.
inactive
The T-SMINT
channel even if no D-channel frame has to be transmitted. It should
be reset when the access has been completed to grant a similar
access to other devices transmitting in that IOM-channel.
4 bit C/I1 channel width
6 bit C/I1 channel width
Interrupt generation ISTA.CIC of CIR0.CIC1is masked
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled
H
H
CODR1
â
IX will try to access the TIC-bus to occupy the C/I-
read
write
162
Register Description
CICW
â
Address:
Address:
IX with TIC-Bus
PEF 81902
2001-11-12
CI1E
0
2F
2F
H
H