PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 64

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits
are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e.
the higher two bits are ignored).
The C/I1 channel is accessed via registers CIR1 and CIX1. The connection of CIR1 and
CIX1 to DD and DU, respectively, can be selected by setting bit HCI_CR.DPS_CI1. A
change in the received C/I1 code is indicated by an interrupt status without double last
look criterion.
CIC Interrupt Logic
Figure 25
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case
the occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one.
Bits CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1.
The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
received C/I channel 0 before the first one has been read, immediately after reading of
CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several
consecutive codes are detected, only the first and the last code are obtained at the first
and second register read, respectively.
For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always
stored in CIR1.
•
Figure 25
Data Sheet
shows the CIC interrupt structure.
CIC Interrupt Structure
MASK
HDLC
WOV
MOS
CIC
TIN
INT
ST
S
U
HDLC
ISTA
WOV
MOS
TIN
CIC
S
ST
U
50
CI1E
CIX1
CIC0
CIC1
CIR0
Functional Description
PEF 81902
2001-11-12