PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 125

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

during transmission the transmitter responds always with a XMR (transmit message
repeat) interrupt and stops transmission.
If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs
out of data then it will assert a XDU (transmit data underrun) interrupt.
Receiver
The reception is IOM
starts in the first selected channel (B1, B2, D, according to the setting of register HCI_CR
in the IOM
are the same as in others modes.
All incoming data bytes are stored in the RFIFO. If the FIFO is full a RFO interrupt is
asserted (EXMR.SRA = ’0’).
Note: In the extended transparent mode the EXMR register has to be set to ’xxx00000‘
2.6.6
The timer provides two modes
is generated only once after expiration of the selected period, and a periodic timer
interrupt, which means an interrupt is generated continuously after every expiration of
that period.
•
Table 28
Address
When the programmed period has expired an interrupt is generated (ISTA.TIN).
The host controls the timer by setting bit CMDR.STI to start the timer and by writing
register TIMR to stop the timer. After time period T1 an interrupt is generated
continuously if CNT=7 or a single interrupt is generated after timer period T if CNT<7
(Figure
Data Sheet
04
H
50).
â
Timer
-2 Handler) of the next IOM
Register
TIMR
Timer
â
-2-frame aligned and byte aligned, like transmission, i.e. reception
Periodic
Count Down
Modes
(Table
28), a count down timer interrupt, i.e. an interrupt
â
-2 frame. The FIFO indications and commands
111
Period
64 ... 2048 ms
2.048 ... 14.336 s
Functional Description
PEF 81902
2001-11-12