PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 200

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

4.7.10
MCDA
Value after reset: FF
MCDAxy Monitoring CDAxy Bits
4.7.11
STI
Value after reset: 00
For all interrupts in the STI register the following logical states are applied
STOVxy
Data Sheet
STOV21 STOV20 STOV11 STOV10
Bit7
7
7
MCDA21
MCDA - Monitoring CDA Bits
Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register.
This can be used for monitoring the D-channel bits on DU and DD and the
“Echo bits” on the TIC bus with the same register.
STI - Synchronous Transfer Interrupt
0 =
1 =
Synchronous Transfer Overflow Interrupt
Enabled STOV interrupts for a certain STIxy interrupt are generated when
the STIxy has not been acknowledged in time via the ACKxy bit in the ASTI
register. This must be one (for DPS = ‘0’) or zero (for DPS = ‘1’) BCL clock
cycles before the time slot which is selected for the STOV.
Bit6
Interrupt has not occurred
Interrupt has occurred
H
H
Bit7
MCDA20
Bit6
read
read
186
STI21
Bit7
MCDA11
STI20
Bit6
Register Description
STI11
Address:
Address:
Bit7
MCDA10
PEF 81902
2001-11-12
STI10
Bit6
0
0
57
58
H
H