PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 201

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

STIxy
Note: ST0Vxy and ACKxy are useful for synchronizing microcontroller accesses and
4.7.12
ASTI
Value after reset: 00
ACKxy
4.7.13
MSTI
Value after reset: FF
For the MSTI register the following logical states are applied:
Data Sheet
STOV21 STOV20 STOV11 STOV10
receive/transmit operations. One BCL clock is equivalent to two DCL clocks.
7
0
7
0 =
Synchronous Transfer Interrupt
Depending on the DPS bit in the corresponding TSDPxy register the
Synchronous Transfer Interrupt STIxy is generated two (for DPS = ‘0’) or
one (for DPS = ‘1’) BCL clock cycles after the selected time slot
(TSDPxy.TSS).
ASTI - Acknowledge Synchronous Transfer Interrupt
Acknowledge Synchronous Transfer Interrupt
After a STIxy interrupt the microcontroller has to acknowledge the interrupt
by setting the corresponding ACKxy bit.
0 =
1 =
MSTI - Mask Synchronous Transfer Interrupt
No activity is initiated
Sets the acknowledge bit ACKxy for a STIxy interrupt
Interrupt is not masked
0
H
H
0
0
write
read/write
187
ACK21
STI21
ACK20
STI20
Register Description
ACK11
STI11
Address:
Address:
PEF 81902
2001-11-12
ACK10
STI10
0
0
58
59
H
H