PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 209

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PEF81902FV1.1

Manufacturer Part Number
PEF81902FV1.1
Description
Manufacturer
Lantiq
Datasheet

Specifications of PEF81902FV1.1

Lead Free Status / RoHS Status
Supplier Unconfirmed
RDS
1 ms
4.9.7
The Interrupt Mask register U-Interface selectively masks each interrupt source in the
ISTAU register by setting the corresponding bit to ’1’.
MASKU
Reset Value: FF
Bit 0..7
4.9.8
FW_VERSION Register contains the Firmware Version number
Data Sheet
7
1
MASKU - Mask Register U-Interface
FW_VERSION
0 =
1 =
Code violation occurred
0 =
1 =
Start of a new frame on the U-interface
useful for synchronization of register accesses by an external µC
0 =
1 =
Mask bits
0 =
1 =
H
CI
6
inactive
CI code change has occurred
inactive
code violation has occurred
inactive
signals the start of a new frame on the U-interface
interrupt active
interrupt masked
RDS
5
4
1
read*
195
)
/write
3
1
2
1
Register Description
Address:
1
1
PEF 81902
2001-11-12
1 ms
0
7B
H

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