PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 112

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

bits of RBCL contain the number of valid bytes in the last data block indicated by RME
(length of last data block
the number of bytes in the last data block or number of complete data blocks,
respectively. If the number of bytes in the last data block is ’0’ the length of the last
received block is equal to the block size.
•
Table 25
The transfer block size (EXMR.RFBS) is 32 bytes by default. If it is necessary to react to
an incoming frame within the first few bytes the microcontroller can set the RFIFO block
size to a smaller value. Each time a CMDR.RMC or CMDR.RRES command is issued,
the RFIFO access controller sets its block size to the value specified in EXMR.RFBS, so
the microcontroller has to write the new value for RFBS before the RMC command.
When setting an initial value for RFBS before the first HDLC activities, a RRES
command must be issued afterwards.
The RFIFO can hold any number of frames fitting in the 64 bytes independent on RFBS.
At the end of a frame, the RSTA byte is always inserted.
All generated interrupts are inserted together with all additional information into a wait
line to be individually passed to the host. For example if several data blocks have been
received to be read by the host and the host acknowledges the current block, a new RPF
or RME interrupt from the wait line is immediately generated to indicate new data.
Data Sheet
EXMR.RFBS
bits
’00’
’01’
’10’
’11’
Receive Byte Count with RBC11...0 in the RBCH and RBCL registers
block size
Selected
32 byte
16 byte
8 byte
4 byte
selected block size).
data blocks in
RBC11...5
RBC11...4
RBC11...3
RBC11...2
complete
98
Table 25
Number of
shows which RBC bits contain
Functional Description
bytes in the last
data block in
RBC4...0
RBC3...0
RBC2...0
RBC1...0
PEF 81902
2001-11-12