PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 186

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

S
MOS
HDLC
Note: A read of the ISTA register clears only the TIN and WOV interrupts. The other
4.6.2
MASK
Value after reset: FF
Bit 7..0
Data Sheet
interrupts are cleared by reading the corresponding status register.
U
7
1 =
S-Transceiver Interrupt
0 =
1 =
MONITOR Status
0 =
1 =
HDLC Interrupt
0 =
1 =
MASK - Mask Register
Mask bits
0 =
1 =
ST
Signals the expiration of the watchdog timer, which means that the
microcontroller has failed to set the watchdog timer control bits
WTC1 and WTC2 (MODE1 register) in the correct manner. A reset
out pulse on pin RSTO has been generated by the T-SMINT
inactive
An interrupt was generated by the S-transceiver. Read the ISTAS
register.
inactive
A change in the MONITOR Status Register (MOSR) has occurred.
inactive
An interrupt originated in the HDLC interrupt sources has been
recognized.
Interrupt is not masked
Interrupt is masked
H
CIC
TIN
write
172
WOV
S
Register Description
MOS
Address:
PEF 81902
2001-11-12
HDLC
â
0
IX.
3C
H