PEF81902FV1.1 Lantiq, PEF81902FV1.1 Datasheet - Page 187

• Manufacturer Part Number: PEF81902FV1.1
• Manufacturer: Lantiq

Specifications of PEF81902FV1.1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Each interrupt source in the ISTA register can be selectively masked by setting the
corresponding bit in MASK to ‘1’. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ‘0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
4.6.3
MODE1
Value after reset: 04
MCLK
CDS
WTC1, 2
Data Sheet
mask bit in MASK is active, but no interrupt is generated.
7
MODE1 - Mode1 Register
Master Clock Frequency
The Master Clock Frequency bits control the microcontroller clock output
depending on MODE1.CDS = ’0’ or ’1’ (Table
00 =
01 =
10 =
11 =
Clock Divider Selection
0 =
1 =
Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (RSS = ‘11’) the
watchdog timer is started. During every time period of 128 ms the
microcontroller has to program the WTC1 and WTC2 bit in the following
sequence
10
MCLK
MODE1.CDS = ’0’
3.84 MHz
0.96 MHz
7.68 MHz
disabled
The 15.36 MHz oscillator clock divided by two is input to the MCLK
prescaler
The 15.36 MHz oscillator clock is input to the MCLK prescaler.
first step
H
(Chapter
CDS
2.2):
WTC1
read/write
173
MODE1.CDS = ’1’
7.68 MHz
1.92 MHz
15.36 MHz
disabled
WTC2
Table
CFS
2.1.3).
Register Description
RSS2
Address:
PEF 81902
2001-11-12
RSS1
0
3D
H