EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 9

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Transceivers
Figure 2–1. Stratix II GX Transceiver Block Diagram
Notes to
(1)
(2)
Altera Corporation
October 2007
Reference
Reference
SIIGX51003-2.2
PMA Analog Section
Clock
Clock
n represents the number of bits in each word that need to be serialized by the transmitter portion of the PMA or have
been deserialized by the receiver portion of the PMA. n = 8, 10, 16, or 20.
m represents the number of bits in the word that pass between the FPGA logic and the PCS portion of the transceiver.
m = 8, 10, 16, 20, 32, or 40.
Deserializer
Transmitter
Figure
Recovery
Serializer
Receiver
Clock
Unit
PLL
PLL
2–1:
(1)
(1)
n
n
PCS Digital Section
Aligner
Word
Stratix
right side of the device, which contains up to 20 high-speed 6.375-Gbps
serial transceiver channels. Each Stratix II GX transceiver block contains
four full-duplex channels and supporting logic to transmit and receive
high-speed serial data streams. The transceivers deliver bidirectional
point-to-point data transmissions, with up to 51 Gbps (6.375 Gbps per
channel) of full-duplex data transmission per transceiver block.
Figure 2–1
within the Stratix II GX device.
Transceivers within each block are independent and have their own set of
dividers. Therefore, each transceiver can operate at different frequencies.
Each block can select from two reference clocks to provide two clock
domains that each transceiver can select from.
Deskew
XAUI
Lane
®
II GX devices incorporate dedicated embedded circuitry on the
8B/10B
Encoder
shows the function blocks that make up a transceiver channel
Matcher
Rate
2. Stratix II GX Architecture
Decoder
8B/10B
Serializer
Byte
Deserializer
Byte
Ordering
Byte
Compensation
FIFO Buffer
Phase
Compensation
FIFO Buffer
Phase
2–1
FPGA Fabric
(2)
(2)
m
m