EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 235

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Altera Corporation
June 2009
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
LVDS
LVPECL
Table 4–54. Timing Measurement Methodology for Input Pins (Part 2 of 2)
Input buffer sees no load at buffer input.
Input measuring point at buffer input is 0.5 V
Output measuring point is 0.5 V
Input edge rate is 1 V/ns.
Less than 50-mV ripple on V
V
CCPD
Table
= 2.97 V, less than 50-mV ripple on V
I/O Standard
4–54:
CCIO
CC
and V
at internal node.
CCPD
V
CCIO
, V
CCIO
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
2.325
3.135
CCIO
CCINT
and V
(V)
.
Measurement Conditions
= 1.15 V with less than 30-mV ripple.
CCPD
, V
V
0.830
0.688
0.688
0.570
1.163
1.163
0.830
0.830
0.688
0.688
0.830
0.830
REF
CCINT
(V)
= 1.15 V.
Stratix II GX Device Handbook, Volume 1
Edge Rate (ns)
DC and Switching Characteristics
1.660
1.375
1.375
1.140
2.325
2.325
1.660
1.660
1.375
1.375
1.660
1.660
0.100
0.100
Notes
(1), (2), (3),
Measurement Point
VMEAS (V)
0.6875
0.6875
1.1625
1.1625
0.6875
0.6875
1.1625
1.5675
0.570
0.83
0.83
0.83
0.83
0.83
(4)
4–65