EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 242

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Timing Model
4–72
Stratix II GX Device Handbook, Volume 1
t
t
t
t
t
t
t
t
t
t
t
t
t
M512RC
M512WERESU
M512WEREH
M512DATASU
M512DATAH
M512WADDRSU
M512WADDRH
M512RADDRSU
M512RADDRH
M512DATACO1
M512DATACO2
M512CLKL
M512CLKH
Table 4–59. M512 Block Internal Timing Microparameters (Part 1 of 2)
Symbol
Synchronous
read cycle time
Write or read
enable setup
time before clock
Write or read
enable hold time
after clock
Data setup time
before clock
Data hold time
after clock
Write address
setup time before
clock
Write address
hold time after
clock
Read address
setup time before
clock
Read address
hold time after
clock
Clock-to-output
delay when using
output registers
Clock-to-output
delay without
output registers
Minimum clock
low time
Minimum clock
high time
Parameter
2089
22
203
22
203
22
203
22
203
298
2102
1315
1315
Min
-3 Speed
Grade(2)
2318
478
2345
Max
-3 Speed Grade
2089
23
213
23
213
23
213
23
213
298
2102
1380
1380
Min
(3)
2433
501
2461
Max
-4 Speed Grade -5 Speed Grade
2089
24
226
24
226
24
226
24
226
298
2102
1468
1468
Min
2587
533
2616
Max
2089
29
272
29
272
29
272
29
272
298
2102
1762
1762
Min
Altera Corporation
3104
640
3141
Max
June 2009
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps