EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 122

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

I/O Structure
Figure 2–78. Column I/O Block Connection to the Interconnect
Note to
(1)
2–114
Stratix II GX Device Handbook, Volume 1
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0]
Figure
Local Interconnect
from Logic Array (1)
Interconnects
R4 & R24
Control Signals
2–78:
I/O Block
32 Data &
Interconnect
LAB
LAB Local
Figure 2–78
.
shows how a column I/O block connects to the logic array.
Vertical I/O Block
Interconnects
C4 & C16
32
LAB
IO_dataina[3..0]
IO_datainb[3..0]
LAB
Vertical I/O
Block Contains
up to Four IOEs
io_clk[7..0]
Altera Corporation
October 2007