EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 108

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EP2SGX90EF1152C3

Manufacturer Part Number
EP2SGX90EF1152C3
Description
Stratix II GX
Manufacturer
Altera
Datasheet

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PLLs and Clock Networks
Figure 2–70. PLL Locations
2–100
Stratix II GX Device Handbook, Volume 1
PLLs
FPLL7CLK
FPLL8CLK
CLK[3..0]
7
1
2
8
Figure 2–70
floorplan.
Figures 2–71
PLL outputs and the side clock pins. The connections to the global and
regional clocks from the fast PLL outputs, internal drivers, and the CLK
pins on the left side of the device are shown in
shows a top-level diagram of the Stratix II GX device and PLL
and
2–72
shows global and regional clocking from the fast
CLK[15..12]
CLK[7..4]
11
12
5
6
Table
2–27.
Altera Corporation
October 2007

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