EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 83

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Figure 2–52. M4K RAM Block LAB Row Interface
Altera Corporation
October 2007
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnect
M4K RAM Block Local
Interconnect Region
16
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■
■
■
■
You cannot use an initialization file to initialize the contents of a M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
datain
control
signals
clocks
LAB Row Clocks
M4K RAM
address
Block
dataout
byte
enable
36
Stratix II GX Device Handbook, Volume 1
6
Stratix II GX Architecture
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnect
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