EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 110

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

PLLs and Clock Networks
Figure 2–72. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL
Outputs
Notes to
(1)
(2)
2–102
Stratix II GX Device Handbook, Volume 1
Clock pins
CLK0p
CLK1p
CLK2p
CLK3p
Left Side Global and Regional
Table 2–27. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs
Clock Network Connectivity
(Part 1 of 3)
The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
EP2SGX30C/D and EP2SGX60C/D devices only have two fast PLLs (1 and 2); they do not contain corner fast
PLLs.
Notes
Figure
(1),
2–72:
(2)
PLL 7
PLL 8
Fast
Fast
C0
C1
C2
C3
C0
C1
C2
C3
v
v
RCLK0
RCLK4
v
v
RCLK1
RCLK5
v
v
RCLK2
RCLK6
v
v
RCLK3
RCLK7
v
GCLK0
v
GCLK1
v
GCLK2
v
GCLK3
v
Altera Corporation
v
October 2007
v
v