EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 100

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

PLLs and Clock Networks
Figure 2–63. Dual-Regional Clocks
Figure 2–64. Hierarchical Clock Networks per Quadrant
2–92
Stratix II GX Device Handbook, Volume 1
PLLs
CLK[3..0]
Regional Clock Network [7..0]
Global Clock Network [15..0]
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources
consisting of 16 global clock lines and 8 regional clock lines. Multiplexers
are used with these clocks to form buses to drive LAB row clocks, column
IOE clocks, or row IOE clocks. Another multiplexer is used at the LAB
level to select three of the six row clocks to feed the ALM registers in the
LAB (see
CLK[15..12]
Figure
2–64).
or Half-Quadrant
Clocks Available
to a Quadrant
Clock [23..0]
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
PLLs
CLK[3..0]
CLK[7..4]
Column I/O Cell
IO_CLK[7..0]
Lab Row Clock [5..0]
Row I/O Cell
IO_CLK[7..0]
Altera Corporation
CLK[15..12]
October 2007