EP2SGX90EF1152C3 Altera, EP2SGX90EF1152C3 Datasheet - Page 47

• Manufacturer Part Number: EP2SGX90EF1152C3
• Description: Stratix II GX
• Manufacturer: Altera

Altera Corporation
October 2007
REFCLK[1..0]
Transmitter PLL
Receiver PLL
Global clock
(driven from an
input pin)
Inter-transceiver
lines
Table 2–11. Available Clocking Connections for Transceivers
Source
Transmitter
PLL
v
v
v
Table 2–11
transceivers.
Clock Resource for PLD-Transceiver Interface
For the regional or global clock network to route into the transceiver, a
local route input output (LRIO) channel is required. Each LRIO clock
region has up to eight clock paths and each transceiver block has a
maximum of eight clock paths for connecting with LRIO clocks. These
resources are limited and determine the number of clocks that can be used
between the PLD and transceiver blocks.
LRIO resources available for Stratix II GX devices with different numbers
of transceiver blocks.
Tables 2–12
to the transceiver block.
Region0
8 LRIO clock
Region1
8 LRIO clock
Table 2–12. Available Clocking Connections for Transceivers in 2SGX30D
Region
Receiver PLL
summarizes the possible clocking connections for the
through
v
v
v
Global
Clock
2–15
v
v
Clock Resource
Global Clock
show the connection of the LRIO clock resource
Destination
RCLK 20-27
RCLK 12-19
v
v
v
Regional
Clock
Stratix II GX Device Handbook, Volume 1
Table 2–12
Regional
8 Clock I/O
Clock
Bank 13
v
v
v
v
Stratix II GX Architecture
Transceiver
shows the number of
Inter-Transceiver
8 Clock I/O
Bank 14
v
Lines
v
2–39