AFS600-FGG484 Actel, AFS600-FGG484 Datasheet - Page 90

• Manufacturer Part Number: AFS600-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG484

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 172
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Architecture
2- 74
The following signals are used to configure the FIFO4K18 memory element:
WW and RW
These signals enable the FIFO to be configured in one of the five allowable aspect ratios
Table 2-33 • Aspect Ratio Settings for WW[2:0]
WBLK and RBLK
These signals are active low and will enable the respective ports when Low. When the RBLK signal is
High, the corresponding port’s outputs hold the previous value.
WEN and REN
Read and write enables. WEN is active low and REN is active high by default. These signals can be
configured as active high or low.
WCLK and RCLK
These are the clock signals for the synchronous read and write operations. These can be driven
independently or with the same driver.
RPIPE
This signal is used to specify pipelined read on the output. A Low on RPIPE indicates a nonpipelined
read, and the data appears on the output in the same clock cycle. A High indicates a pipelined read, and
data appears on the output in the next clock cycle.
RESET
This active low signal resets the output to zero when asserted. It resets the FIFO counters. It also sets all
the RD pins Low, the FULL and AFULL pins Low, and the EMPTY and AEMPTY pins High
Table 2-34 • Input Data Signal Usage for Different Aspect Ratios
WD
This is the input data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. When a data
width less than 18 is specified, unused higher-order signals must be grounded
RD
This is the output data bus and is 18 bits wide. Not all 18 bits are valid in all configurations. Like the WD
bus, high-order bits become unusable if the data width is less than 18. The output data on unused pins is
undefined
ESTOP, FSTOP
ESTOP is used to stop the FIFO read counter from further counting once the FIFO is empty (i.e., the
EMPTY flag goes High). A High on this signal inhibits the counting.
WW2, WW1, WW0
000
001
010
011
100
101, 110, 111
D×W
4k
2k
1k
512
256
×
×
×
1
2
4
×
×
9
18
(Table
2-34).
R e visio n 1
RW2, RW1, RW0
101, 110, 111
000
001
010
100
011
WD[17:1], RD[17:1]
WD[17:2], RD[17:2]
WD[17:4], RD[17:4]
WD[17:9], RD[17:9]
WD/RD Unused
–
(Table
2-34).
Reserved
256×18
512×9
D
4k×1
2k×2
1k×4
(Table
×
(Table
W
2-33).
2-34).