AFS600-FGG484 Actel, AFS600-FGG484 Datasheet - Page 169
![FPGA - Field Programmable Gate Array 600K System Gates](/photos/16/15/161503/landingpageactelfusion-2_sml.jpg)
AFS600-FGG484
Manufacturer Part Number
AFS600-FGG484
Description
FPGA - Field Programmable Gate Array 600K System Gates
Manufacturer
Actel
Datasheet
1.AFS600-PQG208.pdf
(330 pages)
Specifications of AFS600-FGG484
Processor Series
AFS600
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
172
Data Ram Size
110592
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
600 K
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AFS600-FGG484
Manufacturer:
Actel
Quantity:
135
Company:
Part Number:
AFS600-FGG484I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AFS600-FGG484I
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
AFS600-FGG484K
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Figure 2-110 • Timing Diagram (with skew circuit selected)
Weak Pull-Up and Weak Pull-Down Resistors
Fusion devices support optional weak pull-up and pull-down resistors for each I/O pin. When the I/O is
pulled up, it is connected to the V
connected to GND. Refer to
Slew Rate Control and Drive Strength
Fusion devices support output slew rate control: high and low. The high slew rate option is recommended
to minimize the propagation delay. This high-speed option may introduce noise into the system if
appropriate signal integrity measures are not adopted. Selecting a low slew rate reduces this kind of
noise but adds some delays in the system. Low slew rate is recommended when bus transients are
expected. Drive strength should also be selected according to the design requirements and noise
immunity of the system.
The output slew rate and multiple drive strength controls are available in LVTTL/LVCMOS 3.3 V,
LVCMOS 2.5 V, LVCMOS 2.5 V / 5.0 V input, LVCMOS 1.8 V, and LVCMOS 1.5 V. All other I/O
standards have a high output slew rate by default.
For Fusion slew rate and drive strength specifications, refer to the appropriate I/O bank table:
Table 2-80 on page 2-157
that are preset for each I/O standard.
Transmitter 1: OFF
Transmitter 2: ON
•
•
•
Fusion Standard I/O
Fusion Advanced I/O
Fusion Pro I/O
ENABLE (t2)
ENABLE (t1)
EN (b1)
EN (b2)
(Table 2-77 on page
lists the default values for the above selectable I/O attributes as well as those
(Table 2-75 on page
Table 2-94 on page 2-173
(Table 2-76 on page
CCI
Result: No Bus Contention
of its corresponding I/O bank. When it is pulled down, it is
2-154)
R e v i s i o n 1
Transmitter 1: ON
2-154)
2-154)
Transmitter 2: OFF
for more information.
Actel Fusion Family of Mixed Signal FPGAs
Transmitter 1: OFF
2- 153
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