AFS600-FGG484 Actel, AFS600-FGG484 Datasheet - Page 107

• Manufacturer Part Number: AFS600-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG484

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 172
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To initiate a current measurement, the appropriate Current Monitor Strobe (CMSTB) signal on the AB
macro must be asserted low for at least t
CMSTB must be asserted high for at least t
must remain high until after the SAMPLE signal is de-asserted by the AB macro. Note that the minimum
sample time cannot be less than t
with the ADC control signals.
Figure 2-72 • Timing Diagram for Current Monitor Strobe
Figure 2-73
goes into the 10× amplifier and is then converted by the ADC. For example, a current of 1.5 A is drawn
from a 10 V supply and is measured by the voltage drop across a 0.050 Ω sense resistor, The voltage
drop is amplified by ten times by the amplifier and then measured by the ADC. The 1.5 A current creates
a differential voltage across the sense resistor of 75 mV. This becomes 750 mV after amplification. Thus,
the ADC measures a current of 1.5 A as 750 mV. Using an ADC with 8-bit resolution and VAREF of 2.56
V, the ADC result is decimal 75.
where
I is the current flowing through the sense resistor
ADC is the result from the ADC
VAREF is the Reference voltage
N is the number of bits
Rsense is the resistance of the sense resistor
ADCSTART
CMSTBx
illustrates positive current monitor operation. The differential voltage between AV and AC
VADC
t
CMSLO
I
EQ 3
CMSHI
=
(
ADC V
shows how to compute the current from the ADC result.
.
Figure 2-72
CMSLO
×
CMSET
R e v i s i o n 1
AREF
in order to discharge the previous measurement. Then
t
CMSET
prior to asserting the ADCSTART signal. The CMSTB
)
shows the timing diagram of CMSTB in relationship
⁄
ADCSTART can be asserted
after this point to start ADC
sampling.
(
10 2
×
N
t
CMSHI
×
R
Actel Fusion Family of Mixed Signal FPGAs
sense
)
EQ 3
2- 91