AFS600-FGG484 Actel, AFS600-FGG484 Datasheet - Page 219

• Manufacturer Part Number: AFS600-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG484

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 172
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-141 • Minimum and Maximum DC Input and Output Levels
Figure 2-124 • AC Loading
Table 2-142 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-143 • 3.3 V GTL+
3.3 V GTL+
Drive
Strength
35 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.1
Note:
Speed
Grade
Note:
Std.
–1
–2
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
*Measuring point = V
For the derating values at specific junction temperature and voltage supply levels, refer to
page
Commercial Temperature Range Conditions: T
Worst-Case VCCI = 3.0 V, VREF = 1.0 V
t
DOUT
0.66
0.56
0.49
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V.
3-9.
Min.
–0.3
V
Timing Characteristics
Input High (V)
2.06
1.75
1.53
t
VIL
DP
VREF – 0.1 VREF + 0.1
VREF + 0.1
Max.
V
trip
0.04
0.04
0.03
t
DIN
. See
Table 2-87 on page 2-168
1.59
1.35
1.19
t
Min.
PY
V
Measuring Point* (V)
Test Point
VIH
t
EOUT
0.43
0.36
0.32
Max.
1.0
3.6
V
GTL+
2.09
1.78
1.56
t
R e v i s i o n 1
ZL
VTT
Max.
V
J
0.6
for a complete table of trip points.
V
OL
= 70°C, Worst-Case VCC = 1.425 V,
25
10 pF
2.06
1.75
1.53
t
ZH
VREF (typ.) (V)
VOH
Min.
V
–
1.0
t
LZ
Actel Fusion Family of Mixed Signal FPGAs
mA mA
I
35
OL
t
I
HZ
35
OH
V
TT
Max.
mA
I
181
OSL
(typ.) (V)
4.33
3.68
3.23
t
1.5
ZLS
3
Max.
I
mA
268
OSH
t
4.29
3.65
3.20
ZHS
3
Table 3-7 on
C
LOAD
µA
I
10
IL
10
1
4
Units
ns
ns
ns
(pF)
2- 203
µA
I
10
IH
2
4