AFS600-FGG484 Actel, AFS600-FGG484 Datasheet - Page 247

• Manufacturer Part Number: AFS600-FGG484
• Description: FPGA - Field Programmable Gate Array 600K System Gates
• Manufacturer: Actel

Specifications of AFS600-FGG484

• Processor Series: AFS600
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 172
• Data Ram Size: 110592
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 600 K
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

and TRST are equipped with pull-up resistors to ensure proper operation when no input data is supplied
to them. These pins are dedicated for boundary scan test usage. Refer to the
page 2-228
machine (16 states) that operates as shown in
values that must be present on TMS at a rising edge of TCK for the given state transition to occur. IR and
DR indicate that the instruction register or the data register is operating in that state.
Table 2-181 • TRST and TCK Pull-Down Recommendations
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals
for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset
state. To guarantee a reset of the controller from any of the possible states, TMS must remain High for
five TCK cycles. The TRST pin can also be used to asynchronously place the TAP controller in the Test-
Logic-Reset state.
Fusion devices support three types of test data registers: bypass, device identification, and boundary
scan. The bypass register is selected when no other register needs to be accessed in a device. This
speeds up test data transfer to other devices in a test data path. The 32-bit device identification register
is a shift register with four fields (LSB, ID number, part number, and version). The boundary scan register
observes and controls the state of each I/O pin. Each I/O cell has three boundary scan register cells,
each with a serial-in, serial-out, parallel-in, and parallel-out pin.
The serial pins are used to serially connect all the boundary scan register cells in a device into a
boundary scan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are
connected to the internal core logic I/O tile and the input, output, and control ports of an I/O buffer to
capture and load data into the register to control or observe the logic state of each I/O.
VJTAG
VJTAG at 3.3 V
VJTAG at 2.5 V
VJTAG at 1.8 V
VJTAG at 1.5 V
Note:
*Equivalent parallel resistance if more than one device is on JTAG chain.
for pull-up/-down recommendations for TDO and TCK pins. The TAP controller is a 4-bit state
R e v i s i o n 1
Figure 2-144 on page
Tie-Off Resistance*
200 Ω to 1 kΩ
200 Ω to 1 kΩ
500 Ω to 1 kΩ
500 Ω to 1 kΩ
Actel Fusion Family of Mixed Signal FPGAs
2-232. The 1s and 0s represent the
"JTAG Pins" section on
2- 231