MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 74

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
MFRC500_33
Product data sheet
PUBLIC
11.2.2.4 Receiving bit oriented frames
11.2.2.5 Communication errors
Table 132. Return values for bit-collision positions
Parity bits are not counted in the CollPos register because bit-collisions in parity bit occur
after bit-collisions in the data bits. If a collision is detected in the SOF, a frame error is
flagged and no data is sent to the FIFO buffer. In this case, the receiver continues to
monitor the incoming signal. It generates the correct notifications to the microprocessor
when the end of the faulty input stream is detected. This helps the microprocessor to
determine when it is next allowed to send data to the card.
The receiver can manage byte streams with incomplete bytes which result in bit-oriented
frames. To support this, the following values may be used:
RxLastBits[2:0] is only valid if a frame error is not indicated by the FramingErr flag. If
RxAlign[2:0] is not zero and ParityEn is active, the first parity bit is ignored and not
checked.
The first byte containing a single bit from the card is not sent to the microprocessor but
suppressed when If RxAlign[2:0] is set to 7 (see
Remark: Collisions detected at CollPos register bit positions 6, 14, 22, 30 and 38 cannot
be resolved using RxAlign[2:0]. They must be resolved using the control software.
The events which can set error flags are shown in
Collision in bit
SOF
Least Significant Bit (LSB) of the Least Significant Byte (LSByte)
…
Most Significant Bit (MSB) of the LSByte
LSB of second byte
…
MSB of second byte
LSB of third byte
…
•
•
BitFraming register’s RxAlign[2:0] bits select a bit offset for the first incoming byte. For
example, if RxAlign[2:0] = 3, the first 5 bits received are forwarded to the FIFO buffer.
Further bits are packed into bytes and forwarded. After reception, RxAlign[2:0] is
automatically cleared. If RxAlign[2:0] = logic 0, all incoming bits are packed into one
byte.
RxLastBits[2:0] returns the number of bits valid in the last received byte. For example,
if RxLastBits[2:0] evaluates to 5 bits at the end of the received command, the 5 least
significant bits are valid. If the last byte is complete, RxLastBits[2:0] evaluates to zero.
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 15 March 2010
048033
Highly Integrated ISO/IEC 14443 A Reader IC
Section 10.5.2.4 on page
Table
133.
CollPos register value
(Decimal)
0
1
…
9
…
16
17
…
8
MFRC500
© NXP B.V. 2010. All rights reserved.
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