MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 51

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
MFRC500_33
Product data sheet
PUBLIC
10.5.2.7 CRCResultMSB register
10.5.2.8 BitFraming register
MSB of the CRC coprocessor register.
Table 59.
Table 60.
Adjustments for bit oriented frames.
Table 61.
Table 62.
Bit
Symbol
Access
Bit
7 to 0
Bit
Symbol
Access
Bit
7
6 to 4 RxAlign[2:0]
3
2 to 0 TxLastBits[2:0]
Symbol
0
0
Symbol
CRCResultMSB[7:0]
CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit
allocation
CRCResultMSB register bit descriptions
BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation
BitFraming register bit descriptions
R/W
All information provided in this document is subject to legal disclaimers.
7
0
7
Rev. 3.3 — 15 March 2010
Value
-
000
001
...
111
-
-
6
6
048033
Description
gives the CRC register’s most significant byte value; only valid if
CRCReady = logic 1.
The register’s value is undefined for 8-bit CRC calculation.
RxAlign[2:0]
Description
reserved
defines the bit position in the FIFO buffer for the first bit received
and stored. Additional received bits are stored in the next
subsequent bit positions. After reception, RxAlign[2:0] is
automatically cleared. For example:
reserved
defines the number of bits of the last byte that shall be
transmitted. 000 indicates that all bits of the last byte will be
transmitted. TxLastBits[2:0] is automatically cleared after
transmission.
the LSB of the received bit is stored in bit position 0 and the
second received bit is stored in bit position 1
the LSB of the received bit is stored in bit position 1, the
second received bit is stored in bit position 2
the LSB of the received bit is stored in bit position 7, the
second received bit is stored in the next byte in bit position 0
D
5
5
Highly Integrated ISO/IEC 14443 A Reader IC
CRCResultMSB[7:0]
4
4
R
3
R/W
3
0
2
2
TxLastBits[2:0]
MFRC500
© NXP B.V. 2010. All rights reserved.
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0
0