MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 31

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
MFRC500_33
Product data sheet
PUBLIC
9.10.2.1 Automatic Q-clock calibration
9.10.2 Receiver operation
The signal can be observed on its way through the receiver as shown in
signal at a time can be routed to pin AUX using the TestAnaSelect register as described in
Section 15.2.2 on page
In general, the default settings programmed in the StartUp initialization file are suitable for
use with the MFRC500 to MIFARE card data communication. However, in some
environments specific user settings will achieve better performance.
The quadrature demodulation concept of the receiver generates a phase signal (I-clock)
and a 90° phase-shifted quadrature signal (Q-clock). To achieve the optimum
demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90°. After
the reset phase, a calibration procedure is automatically performed.
Automatic calibration can be set-up to execute at the end of each Transceive command if
bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations
except after the reset sequence. Automatic calibration can also be triggered by the
software when bit ClkQCalib has a logic 0 to logic 1 transition.
Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or
approximately 4.8 μs.
The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift
between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the
phase-shift between the Q-clock and the I-clock is greater than 180°.
Remark:
Fig 11. Automatic Q-clock calibration
•
•
•
The StartUp configuration file enables automatic Q-clock calibration after a reset
If bit ClkQCalib = logic 1, automatic calibration is not performed. Leaving this bit set to
logic 1 can be used to permanently disable automatic calibration.
It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The
aim could be to disable automatic calibration and set the delay using the software.
Configuring the delay value using the software requires bit ClkQCalib to have been
previously set to logic 1 and a time interval of at least 4.8 μs has elapsed. Each delay
value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the
configured delay value is overwritten by the next automatic calibration interval.
All information provided in this document is subject to legal disclaimers.
Transceive command
from reset sequence
calibration impulse
calibration impulse
Rev. 3.3 — 15 March 2010
96.
from end of
048033
ClkQCalib bit
Highly Integrated ISO/IEC 14443 A Reader IC
a rising edge initiates
Q-clock calibration
001aak616
MFRC500
© NXP B.V. 2010. All rights reserved.
Figure
10. One
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