MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 47

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
MFRC500_33
Product data sheet
PUBLIC
10.5.1.7 InterruptEn register
10.5.1.8 InterruptRq register
Control bits to enable and disable passing of interrupt requests.
Table 45.
Table 46.
[1]
Interrupt request flags.
Table 47.
Table 48.
Bit
Symbol
Access
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
Access
Bit Symbol
7
6
5
4
3
This bit can only be set or cleared using bit SetIEn.
SetIRq
0
TimerIRq
TxIRq
RxIRq
Symbol
SetIEn
0
TimerIEn
TxIEn
RxIEn
IdleIEn
HiAlertIEn -
LoAlertIEn -
InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation
InterruptEn register bit descriptions
InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation
InterruptRq register bit descriptions
SetIEn
SetIRq
W
W
7
7
All information provided in this document is subject to legal disclaimers.
Value
1
0
-
-
-
-
-
1
Value
1
0
-
1
0
0
1
0
R/W
R/W
Rev. 3.3 — 15 March 2010
6
0
6
0
Description
indicates that the marked bits in the InterruptEn register are set
clears the marked bits
reserved
sends the TimerIRq timer interrupt request to pin IRQ
sends the TxIRq transmitter interrupt request to pin IRQ
sends the RxIRq receiver interrupt request to pin IRQ
sends the IdleIRq idle interrupt request to pin IRQ
sends the HiAlertIRq high alert interrupt request to pin IRQ
sends the LoAlertIRq low alert interrupt request to pin IRQ
Description
sets the marked bits in the InterruptRq register
clears the marked bits in the InterruptRq register
reserved
timer decrements the TimerValue register to zero
timer decrements are still greater than zero
TxIRq is set to logic 1 if one of the following events occurs:
when not acted on by Transceive, Authent1, Authent2, WriteE2 or
CalcCRC commands
reception still ongoing
the receiver terminates
TimerIRq
TimerIEn
Transceive command; all data transmitted
Authent1 and Authent2 commands; all data transmitted
WriteE2 command; all data is programmed
CalcCRC command; all data is processed
048033
R/W
D
5
5
TxIRq
TxIEn
Highly Integrated ISO/IEC 14443 A Reader IC
R/W
D
4
4
RxIEn
RxIRq
R/W
D
3
3
IdleIEn HiAlertIEn LoAlertIEn
IdleIRq HiAlertIRq LoAlertIRq
R/W
D
2
2
MFRC500
[1]
R/W
© NXP B.V. 2010. All rights reserved.
1
D
1
[1]
[1]
[1]
[1]
[1]
R/W
47 of 110
D
0
0