MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 14

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
MFRC500_33
Product data sheet
PUBLIC
Fig 6.
Master key byte
Master key bits
EEPROM byte
Example
address
Key storage format
9.2.3.2 Storage of keys in the EEPROM
9.3.1.1 Access rules
9.3.1 Accessing the FIFO buffer
9.3 FIFO buffer
k7 k6 k5 k4 k7 k6 k5 k4
5Ah
Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is
shown in
Example: The value for the key must be written to the EEPROM.
Remark: It is possible to load data for other key formats into the EEPROM key storage
location. However, it is not possible to validate card authentication with data which will
cause the LoadKeyE2 command (see
The MFRC500 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No
memory segmentation is used to mirror the 12-byte structure of key storage. Thus, every
byte of the dedicated memory area can be the start of a key.
Example: If the key loading cycle starts at the last byte address of an EEPROM block, (for
example, key byte 0 is stored at 12Fh), the next bytes are stored in the next EEPROM
block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13Ah.
Based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32
different keys can be stored in the EEPROM.
Remark: It is not possible to load a key exceeding the EEPROM byte location 1FFh.
An 8 × 64 bit FIFO buffer is used in the MFRC500 to act as a parallel-to-parallel converter.
It buffers both the input and output data streams between the microprocessor and the
internal circuitry of the MFRC500. This makes it possible to manage data streams up to
64 bytes long without needing to take timing constraints into account.
The FIFO buffer input and output data bus is connected to the FIFOData register. Writing
to this register stores one byte in the FIFO buffer and increments the FIFO buffer write
pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO
buffer read pointer and increments the FIFO buffer read pointer. The distance between the
write and read pointer can be obtained by reading the FIFOLength register.
n
•
•
If the key was: A0h A1h A2h A3h A4h A5h then
5Ah F0h 5Ah E1h 5Ah D2h 5Ah C3h 5Ah B4h 5Ah A5h would be written.
0 (LSB)
k3 k2 k1 k0 k3 k2 k1 k0
Figure
n + 1
F0h
All information provided in this document is subject to legal disclaimers.
6.
Rev. 3.3 — 15 March 2010
k7 k6 k5 k4 k7 k6 k5 k4
n + 2
5Ah
048033
1
k3 k2 k1 k0 k3 k2 k1 k0
Section 11.6.1 on page
Highly Integrated ISO/IEC 14443 A Reader IC
n + 3
E1h
k7 k6 k5 k4 k7 k6 k5 k4
n + 10
5Ah
81) to fail.
5 (MSB)
MFRC500
k3 k2 k1 k0 k3 k2 k1 k0
© NXP B.V. 2010. All rights reserved.
n + 11
A5h
001aak640
14 of 110