MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 104

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Byte assignment for register initialization at
Table 11. Shipment content of StartUp
Table 12. Byte assignment for register initialization at
Table 13. FIFO buffer access . . . . . . . . . . . . . . . . . . . . .15
Table 14. Associated FIFO buffer registers and flags . . .16
Table 15. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .17
Table 16. Interrupt control registers . . . . . . . . . . . . . . . .17
Table 17. Associated Interrupt request system registers
Table 18. Associated timer unit registers and flags . . . . .23
Table 19. Signal on pins during Hard power-down . . . . .23
Table 20. Pin TX1 configurations . . . . . . . . . . . . . . . . . .27
Table 21. Pin TX2 configurations . . . . . . . . . . . . . . . . . .27
Table 22. TX1 and TX2 source resistance of n-channel
Table 23. Gain factors for the internal amplifier . . . . . . . .32
Table 24. DecoderSource[1:0] values . . . . . . . . . . . . . . .34
Table 25. ModulatorSource[1:0] values . . . . . . . . . . . . . .34
Table 26. MFOUTSelect[2:0] values . . . . . . . . . . . . . . . .34
Table 27. Register settings to enable use of the analog
Table 28. Dedicated address bus: assembling the
Table 29. Multiplexed address bus: assembling the
Table 30. Behavior and designation of register bits . . . . .38
Table 31. MFRC500 register overview . . . . . . . . . . . . . .39
Table 32. MFRC500 register flags overview . . . . . . . . . .41
Table 33. Page register (address: 00h, 08h, 10h, 18h,
Table 34. Page register bit descriptions . . . . . . . . . . . . .43
Table 35. Command register (address: 01h)
MFRC500_33
Product data sheet
PUBLIC
Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Supported microprocessor and EPP interface
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Connection scheme for detecting the parallel
interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8
EEPROM memory organization diagram . . . . .10
Product information field byte allocation . . . . . 11
Product information field byte description . . . . 11
start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
configuration file . . . . . . . . . . . . . . . . . . . . . . .12
startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
driver transistor against
GsCfgCW or GsCfgMod . . . . . . . . . . . . . . . . .28
circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
register address . . . . . . . . . . . . . . . . . . . . . . . .37
register address . . . . . . . . . . . . . . . . . . . . . . . .37
20h, 28h, 30h, 38h) reset value: 1000 0000b,
80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .43
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Product type identification definition . . . . . . . . 11
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 15 March 2010
048033
Table 36. Command register bit descriptions . . . . . . . . . 44
Table 37. FIFOData register (address: 02h)
Table 38. FIFOData register bit descriptions . . . . . . . . . 44
Table 39. PrimaryStatus register (address: 03h)
Table 40. PrimaryStatus register bit descriptions . . . . . . 45
Table 41. FIFOLength register (address: 04h)
Table 42. FIFOLength bit descriptions . . . . . . . . . . . . . . 46
Table 43. SecondaryStatus register (address: 05h)
Table 44. SecondaryStatus register bit descriptions . . . . 46
Table 45. InterruptEn register (address: 06h)
Table 46. InterruptEn register bit descriptions . . . . . . . . 47
Table 47. InterruptRq register (address: 07h)
Table 48. InterruptRq register bit descriptions . . . . . . . . 47
Table 49. Control register (address: 09h)
Table 50. Control register bit descriptions . . . . . . . . . . . 48
Table 51. ErrorFlag register (address: 0Ah)
Table 52. ErrorFlag register bit descriptions . . . . . . . . . . 49
Table 53. CollPos register (address: 0Bh)
Table 54. CollPos register bit descriptions . . . . . . . . . . . 50
Table 55. TimerValue register (address: 0Ch)
Table 56. TimerValue register bit descriptions . . . . . . . . 50
Table 57. CRCResultLSB register (address: 0Dh)
Table 58. CRCResultLSB register bit descriptions . . . . . 50
Table 59. CRCResultMSB register (address: 0Eh)
Table 60. CRCResultMSB register bit descriptions . . . . 51
Table 61. BitFraming register (address: 0Fh)
Table 62. BitFraming register bit descriptions . . . . . . . . . 51
Table 63. TxControl register (address: 11h)
Table 64. TxControl register bit descriptions . . . . . . . . . 52
Table 65. CwConductance register (address: 12h)
Table 66. CwConductance register bit descriptions . . . . 53
Table 67. PreSet13 register (address: 13h)
Highly Integrated ISO/IEC 14443 A Reader IC
reset value: x000 0000b, x0h bit allocation . . . 44
reset value: xxxx xxxxb, xxh bit allocation . . . 44
reset value: 0000 0101b, 05h bit allocation . . 45
reset value: 0000 0000b, 00h bit allocation . . 46
reset value: 01100 000b, 60h bit allocation . . . 46
reset value: 0000 0000b, 00h bit allocation . . 47
reset value: 0000 0000b, 00h bit allocation . . 47
reset value: 0000 0000b, 00h bit allocation . . 48
reset value: 0100 0000b, 40h bit allocation . . 49
reset value: 0000 0000b, 00h bit allocation . . 50
reset value: xxxx xxxxb, xxh bit allocation . . . 50
reset value: xxxx xxxxb, xxh bit allocation . . . 50
reset value: xxxx xxxxb, xxh bit allocation . . . 51
reset value: 0000 0000b, 00h bit allocation . . 51
reset value: 0101 1000b, 58h bit allocation . . 52
reset value: 0011 1111b, 3Fh bit allocation . . . 53
MFRC500
© NXP B.V. 2010. All rights reserved.
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