71M6534-IGT/F Maxim Integrated Products, 71M6534-IGT/F Datasheet - Page 79

IC ENERY METER 3PH 128K 120-LQFP

71M6534-IGT/F

Manufacturer Part Number
71M6534-IGT/F
Description
IC ENERY METER 3PH 128K 120-LQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of 71M6534-IGT/F

Mounting Style
SMD/SMT
Package / Case
LQFP-120
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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FDS_6533_6534_004
5 Firmware Interface
5.1 I/O RAM and SFR Map –Functional Order
In
effect, and reading them always returns zero. Reserved bits may be in use and should not be changed from the values given in parentheses.
Writing values other than those shown in parenthesis to reserved bits may have undesirable side effects and must be avoided.
Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected to the
VBAT pin.
This table lists only the SFR registers that are not generic 8051 SFR registers. Bits marked with † (e.g. UMUX_E
Rev 2
Configuration:
Interrupts and WD Timer:
CE0
CE1
CE2
COMP0
CONFIG0
CONFIG1
VERSION
CONFIG2
CE3
CE5
WAKE
TMUX
ANACTRL
CONFIG3
CONFIG4
INTBITS
IFLAGS
CE4
Table
Name
53, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits have no memory storage, writing them has no
Address
2000
2001
2002
2003
2004
2005
2006
2007
209D
20A8
20A9
20AA
20AB
20AC
20AD
SFR F8
SFR E8
20A7
IE_PLLFALL
WAKE_ARM
VREF_CAL
WD_RST
R (0)
Bit 7
PRE_SAMPS[1:0]
U
U
U
U
U
OPT_TXE[1:0]
U
IE_PLLRISE
EQU[2:0]
PLS_INV
PLL_OK
SLEEP
Bit 6
INT6
R(0)
U
U
U
U
R (0000)
Table 53: I/O RAM Map – Functional Order
LCD_ONLY
IE_WAKE
ECK_DIS
SEL_IDN
SEL_IBN
EX_PLL
Bit 5
INT5
U
U
U
U
CHOP_E[1:0]
EX_FWCOL
CKOUT_E
CHOP_ID
CHOP_IB
M26MHZ
IE_PB
CE_E
Bit 4
INT4
U
U
U
BOOT_SIZE[7:0]
CE_LCTN[7:0]
VERSION[7:0]
IE_FWCOL1
WAKE_RES
VREF_DIS
CE10MHZ
RTM_E
ADC_E
Bit 3
INT3
SUM_CYCLES[5:0]
U
U
U
FIR_LEN[1:0]
LCD_DAC[2:0]
IE_FWCOL0
TMUX[4:0]
MUX_ALT
WD_OVF
71M6533/G/H and 71M6534/H Data Sheet
Bit 2
INT2
U
U
U
MUX_DIV[3:0]
) apply to the 71M6534 only.
WAKE_PRD[2:0]
MPU_DIV[2:0]
SEL_ICN
SEL_IAN
EX_RTC
IE_RTC
Bit 1
INT1
U
U
U
OPT_FDC[1:0]
CHOP_I_EN
COMPSTAT
CHOP_IA
CHOP_IC
M40MHZ
IE_XFER
EX_XFR
Bit 0
INT0
79

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