71M6534-IGT/F Maxim Integrated Products, 71M6534-IGT/F Datasheet - Page 34

• Manufacturer Part Number: 71M6534-IGT/F
• Description: IC ENERY METER 3PH 128K 120-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6534-IGT/F

• Mounting Style: SMD/SMT
• Package / Case: LQFP-120
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

†
even though they are not actually related to an interrupt. These bits are set by hardware when the MPU
wakes from a push button or wake timeout. The bits are reset by writing a zero. Note that the PB flag is
set whenever the PB is pushed, even if the part is already awake.
WD_NROVF_FLAG is set approximately 1 ms before a WDT reset occurs. The flag can be cleared by
writing a zero to it and is automatically cleared by the falling edge of WAKE.
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 33)
If requests of the same priority level are received simultaneously, an internal polling sequence as shown
in
34
The AUTOWAKE and PB flag bits are shown in
EX_XFER
EX_RTC
IEN_WD_NROVF
IEN_SPI
EX_FWCOL
EX_PLL
Table 35
Name
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Interrupt Enable
by setting or clearing one bit in the SFR interrupt priority register IP0 and one in IP1
determines which request is serviced first.
2002[0]
2002[1]
20B0[0]
20B0[4]
2007[4]
2007[5]
Location
Table 32: Interrupt Priority Level Groups
IP1[x]
0
0
1
1
Table 33: Interrupt Priority Levels
IE_XFER
IE_RTC
WD_NROVF_FLAG
SPI_FLAG
IE_FWCOL0
IE_FWCOL1
IE_PLLRISE
IE_PLLFALL
IE_WAKE
IE_PB
0
1
2
3
4
5
External interrupt 0, Serial
channel 1 interrupt
Timer 0 interrupt, External
interrupt 2
External interrupt 1, External
interrupt 3
Timer 1 interrupt, External
interrupt 4
Serial channel 0 interrupt,
External interrupt 5
External interrupt 6
Name
IP0[x]
Interrupt Flag
Table 31
Group Members
0
1
0
1
Level 0 (lowest)
Level 1
Level 2
Level 3 (highest)
because they behave similarly to interrupt flags,
SFR E8[0]
SFR E8[1]
20B1[0]
20B1[4]
SFR E8[3]
SFR E8[2]
SFRE8[6]
SFRE8[7]
SFRE8[5]
SFRE8[4]
Table
Location
Priority Level
32:
Interrupt Description
XFER_BUSY interrupt (INT 6)
RTC_1SEC interrupt (INT 6)
WDT near overflow (INT 6)
SPI Interface (INT2)
FWCOL0 interrupt (INT 2)
FWCOL1 interrupt (INT 2)
PLL_OK rise interrupt (INT 4)
PLL_OK fall interrupt (INT 4)
AUTOWAKE flag
PB flag
†
†
(Table
Rev 2
34).