MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 755

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

J
JTAG
Freescale Semiconductor
interrupts
memory map 10-4
operation
registers
block diagram 31-1
electrical characteristics
features 31-2
initialization 31-9
instructions
low-power modes 7-13
memory map 31-4
overview 31-1
registers
ColdFire Flash module 6-23
debug 2-21
FlexCAN 25-17
overview 10-1
PIT 19-7
prioritization 10-4
QADC
recognition 10-3
sources 10-13
vector determination 10-4
general 10-2
low-power modes 7-9
(IACKLPRn) 10-11
interrupt control (ICRnx) 10-12
interrupt force high/low (INTFRCHn, INTFRCLn) 10-9
interrupt pending high/low (IPRHn, IPRLn) 10-6
interrupt request level (IRLRn) 10-11
mask high/low (IMRHn, n) 10-7
boundary scan timing 33-25
nonscan chain operation 31-9
restrictions 31-9
BYPASS 31-9
CLAMP 31-9
ENABLE_TEST_CTRL 31-8
EXTEST 31-7
HIGHZ 31-8
IDCODE 31-7
LOCKOUT_RECOVERY 31-8
SAMPLE/PRELOAD 31-7
TEST_LEAKAGE 31-8
boundary scan 31-5
bypass 31-5
IDCODE 31-4
instruction shift (IR) 31-4
operation 28-68
sources 28-68
,
30-37
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
L
Listen-only mode 25-12
LOCKOUT_RECOVERY instruction 31-8
Lowest buffer transmitted first (LBUF) 25-21
Low-power modes
M
MAPGA package 32-9
Memory map
TAP controller 31-6
timing diagrams
doze 7-6
peripheral behavior
run 7-5
stop 7-6
summary 7-13
wait 7-6
chip configuration module 27-3
clock module 9-5
JTAG_CFM_CLKDIV 31-5
TEST_CTRL 31-5
BKPT timing 33-27
boundary scan 33-26
test access port 33-26
test clock input 33-26
TRST timing 33-27
chip configuration module 7-9
chip select module 7-7
clock module 7-10
ColdFire Flash module 7-7
core 7-6
debug 7-13
DMA controller 7-7
DMA timers 7-8
EPORT 7-10
Ethernet 7-9
FlexCAN 7-11
general purpose timers 7-11
GPIO 7-9
I
interrupt controller 7-9
JTAG 7-13
modules 7-8
programmable interrupt timers 7-10
QADC 7-11
QSPI 7-8
reset controller 7-9
SCM 7-7
SDRAM controller 7-7
SRAM 7-6
watchdog timer 7-10
2
C 7-8
,
7-13
Index-7