MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 314

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Fast Ethernet Controller (FEC)
17.2
The primary operational modes are described in this section.
17.2.1
Full duplex mode is for use on point-to-point links between switches or end node to switch. Half duplex
mode works in connections between an end node and a repeater or between repeaters. TCR[FDEN]
controls duplex mode selection.
When configured for full duplex mode, flow control may be enabled. Refer to the
TCR[RFC_PAUSE,TFC_PAUSE] bits, the RCR[FCE] bit, and
Control,” for more details.
17.2.2
The following interface options are supported. A detailed discussion of the interface configurations is
provided in
17.2.2.1
The IEEE 802.3 standard defines the media independent interface (MII) for 10/100 Mbps operation. The
MAC-PHY interface may be configured to operate in MII mode by setting RCR[MII_MODE].
FEC_TXCLK and FEC_RXCLK pins driven by the external transceiver determine the operation speed.
The transceiver auto-negotiates the speed or software controls it via the serial management interface
(FEC_MDC/FEC_MDIO pins) to the transceiver. Refer to the MMFR and MSCR register descriptions, as
well as the section on the MII, for a description of how to read and write registers in the transceiver via
this interface.
17.2.2.2
The FEC supports 7-wire interface used by many 10 Mbps Ethernet transceivers. The RCR[MII_MODE]
bit controls this functionality. If this bit is cleared, MII mode is disabled and the 10 Mbps 7-wire mode is
enabled.
17.2.3
The address options supported are promiscuous, broadcast reject, individual address (hash or exact match),
and multicast hash match. Address recognition options are discussed in detail in
Address Recognition.”
17.2.4
Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in
Section 17.5.14, “MII Internal and External Loopback.”
17-4
Modes of Operation
Full and Half Duplex Operation
Interface Options
Section 17.5.6, “Network Interface Options.”
Address Recognition Options
Internal Loopback
10 Mbps and 100 Mbps MII Interface
10 Mpbs 7-Wire Interface Operation
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Section 17.5.11, “Full Duplex Flow
Section 17.5.9, “Ethernet
Freescale Semiconductor