MCF5214CVF66 Freescale Semiconductor, MCF5214CVF66 Datasheet - Page 199

• Manufacturer Part Number: MCF5214CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.3.3
The INTFRCHn and INTFRCLn registers are each 32 bits in size and provide a mechanism to allow
software generation of interrupts for each possible source for functional or debug purposes. The system
design may reserve one or more sources to allow software to self-schedule interrupts by forcing one or
more of these bits (1 = force request, 0 = negate request) in the appropriate INTFRCn register. The
assertion of an interrupt request via the INTFRCn register is not affected by the interrupt mask register.
The INTFRCn register is cleared by reset.
Freescale Semiconductor
31–1
Bits
0
Interrupt Force Registers (INTFRCHn, INTFRCLn)
If an interrupt source is being masked in the interrupt controller mask
register (IMR) or a module’s interrupt mask register while the interrupt
mask in the status register (SR[I]) is set to a value lower than the interrupt’s
level, a spurious interrupt may occur. This is because by the time the status
register acknowledges this interrupt, the interrupt has been masked. A
spurious interrupt is generated because the CPU cannot determine the
interrupt source. To avoid this situation for interrupts sources with levels
1-6, first write a higher level interrupt mask to the status register, before
setting the mask in the IMR or the module’s interrupt mask register. After
the mask is set, return the interrupt mask in the status register to its previous
value. Since level seven interrupts cannot be disabled in the status register
prior to masking, use of the IMR or module interrupt mask registers to
disable level seven interrupts is not recommended.
INT_MASK
MASKALL
Name
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Interrupt mask. Each bit corresponds to an interrupt source. The corresponding
IMRLn bit determines whether an interrupt condition can generate an interrupt.
The corresponding IPRLn bit reflects the state of the interrupt signal even if the
corresponding IMRLn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
Mask all interrupts. Setting this bit will force the other 63 bits of the IMRHn and
IMRLn to ones, disabling all interrupt sources, and providing a global mask-all
capability.
Table 10-7. IMRLn Field Descriptions
NOTE
Description
Interrupt Controller Modules
10-9