MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 966

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Development Support
23-52
1
2
Serialize
Control
Refer to
MPC562/MPC564 only.
29:31
Bits
(SER)
20
21
22
23
24
25
26
27
28
0
0
0
0
Appendix A, “MPC562/MPC564 Compression
Mnemonic
ISCT_SER
DIWP0EN
DIWP1EN
DIWP2EN
DIWP3EN
SIWP0EN
SIWP1EN
SIWP2EN
SIWP3EN
Instruction
(ISCTL)
IFM
Fetch
00
01
10
11
Software trap enable selection of
the 1st I-bus watchpoint
Software trap enable selection of
the 2nd I-bus watchpoint
Software trap enable selection of
the 3rd I-bus watchpoint
Software trap enable selection of
the 4th I-bus watchpoint
Development port trap enable
selection of the 1st I-bus
watchpoint (read only bit)
Development port trap enable
selection of the 2nd I-bus
watchpoint (read only bit)
Development port trap enable
selection of the 3rd I-bus
watchpoint (read only bit)
Development port trap enable
selection of the 4th I-bus
watchpoint (read only bit)
Ignore first match, only for I-bus
breakpoints
RCPU serialize control and
Instruction fetch show cycle
RCPU is fully serialized and show cycles will be performed for all fetched instructions (reset
value)
RCPU is fully serialized and show cycles will be performed for all changes in the program flow
RCPU is fully serialized and show cycles will be performed for all indirect changes in the
program flow
RCPU is fully serialized and no show cycles will be performed for fetched instructions
Table 23-26. ICTRL Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Description
Table 23-27. ISCT_SER Bit Descriptions
Features,” for code compression-specific functionality.
0 = trap disabled (reset value)
1 = trap enabled
0 = trap disabled (reset value)
1 = trap enabled
0 = Do not ignore first match, used for “go to x” (reset value)
1 = Ignore first match (used for “continue”)
These bits control serialization and instruction fetch show
cycles. See
NOTE: Changing the instruction show cycle programming
starts to take effect only from the second instruction after
the actual mtspr to ICTRL.
Non-compressed mode
Functions Selected
Table 23-27
Function
for the bit definitions.
1
Compressed Mode
Freescale Semiconductor
2