MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 450

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

L-Bus to U-Bus Interface (L2U)
11.8.4
The L2U region base address register (L2U_RBAx) defines the base address of a specific region protected
by the data memory protection unit. There are four registers (x = 0...3), one for each supported region.
11-14
Bits
3:31
1:2
Reset
Reset
Reset
Reset
0
Field
Field
Addr
Field
Field
Addr
Region Base Address Registers (L2U_RBAx)
MSB
SP
MSB
LSHOW
16
0
16
Name
0
SP
—
Undefined
17
LSHOW
1
17
1
RBA
Figure 11-5. L2U Region x Base Address Register (L2U_RBAx)
CALRAM Protection (SP) bit is used to protect the CALRAM on the L-bus from U-bus accesses.
Any attempt to set or clear the SP bit from the U-bus side has no affect.
Once this bit is set, the L2U blocks all CALRAM accesses initiated by the U-bus masters and the
access is terminated with a data error on the U-bus.
If L-bus show cycles are enabled, setting this bit will disable L-bus CALRAM show cycles.
LSHOW bits are used to configure the show cycle mode for cycles accessing the L-bus slave e.g.
CALRAM
00 Disable show cycles
01 Show address and data of all L-bus space write cycles
10 Reserved
11 Show address and data of all L-bus space read and write cycles
Reserved
Figure 11-4. L2U Module Configuration Register (L2U_MCR)
18
2
18
2
19
3
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 11-7. L2U_MCR Bit Descriptions
20
20
4
4
21
21
5
5
0000_0000_0000_0000
0000_0000_0000_0000
22
22
6
6
SPR 792–795
Undefined
23
SPR 568
23
7
7
RBA
—
Description
24
24
8
8
0000_0000_0000
—
25
25
9
9
—
10
26
10
26
11
27
11
27
12
28
12
28
Freescale Semiconductor
13
29
13
29
14
30
14
30
LSB
LSB
15
31
15
31