MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 49

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

15-15
15-16
15-17
15-18
15-19
15-20
15-21
15-22
15-23
15-24
15-25
15-26
15-27
15-28
15-29
15-30
15-31
15-32
15-33
15-34
15-35
15-36
15-37
15-38
15-39
15-40
15-41
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
Freescale Semiconductor
Figure
Number
QSPI Status Register (SPSR)................................................................................................ 15-21
QSPI RAM............................................................................................................................ 15-23
CR[0:F] — Command RAM 0x30 51C0, 0x30 51DF.......................................................... 15-24
Flowchart of QSPI Initialization Operation.......................................................................... 15-28
Flowchart of QSPI Master Operation (Part 1) ...................................................................... 15-29
Flowchart of QSPI Master Operation (Part 2) ...................................................................... 15-30
Flowchart of QSPI Master Operation (Part 3) ...................................................................... 15-31
Flowchart of QSPI Slave Operation (Part 1) ........................................................................ 15-32
Flowchart of QSPI Slave Operation (Part 2) ........................................................................ 15-33
SCI Transmitter Block Diagram ........................................................................................... 15-43
SCI Receiver Block Diagram ............................................................................................... 15-44
SCCxR0 — SCI Control Register 0 ..................................................................................... 15-46
SCI Control Register 1 (SCCxR1)........................................................................................ 15-47
SCIx Status Register (SCxSR).............................................................................................. 15-49
SCI Data Register (SCxDR) ................................................................................................. 15-51
Start Search Example............................................................................................................ 15-57
QSCI1 Control Register (QSCI1CR).................................................................................... 15-60
QSCI1 Status Register (QSCI1SR)....................................................................................... 15-61
Queue Transmitter Block Enhancements ............................................................................. 15-63
Queue Transmit Flow ........................................................................................................... 15-66
Queue Transmit Software Flow ............................................................................................ 15-66
Queue Transmit Example for 17 Data Bytes ........................................................................ 15-67
Queue Transmit Example for 25 Data Frames ..................................................................... 15-69
Queue Receiver Block Enhancements .................................................................................. 15-70
Queue Receive Flow ............................................................................................................. 15-73
Queue Receive Software Flow ............................................................................................. 15-74
Queue Receive Example for 17 Data Bytes.......................................................................... 15-75
TouCAN Block Diagram ........................................................................................................ 16-1
Typical CAN Network............................................................................................................ 16-3
Extended ID Message Buffer Structure .................................................................................. 16-4
Standard ID Message Buffer Structure ................................................................................... 16-4
Relationship between System Clock and CAN Bit Segments ................................................ 16-9
CAN Controller State Diagram............................................................................................. 16-12
Interrupt Levels on IRQ with ILBS ...................................................................................... 16-21
TouCAN Message Buffer Memory Map .............................................................................. 16-24
TouCAN Module Configuration Register (CANMCR) ....................................................... 16-25
TouCAN Interrupt Configuration Register (CANICR) ........................................................ 16-27
Control Register 0 (CANCTRL0)......................................................................................... 16-27
Control Register 1 (CANCTRL1)......................................................................................... 16-28
Prescaler Divide Register...................................................................................................... 16-29
MPC561/MPC563 Reference Manual, Rev. 1.2
Figures
Title
Number
Page
xlix