MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 490

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

QADC64E Legacy Mode Operation
A queue is in the active state when a valid queue operating mode is selected, when the selected trigger
event has occurred, or when the QADC64E is performing a conversion specified by a CCW from that
queue.
Only one queue can be active at a time. Either or both queues can be in the paused state. A queue is paused
when the previous CCW executed from that queue had the pause bit set. The QADC64E does not execute
any CCWs from the paused queue until a trigger event occurs. Consequently, the QADC64E can service
queue 2 while queue 1 is paused.
Only queue 2 can be in the suspended state. When a trigger event occurs on queue 1 while queue 2 is
executing, the current queue 2 conversion is aborted. The queue 2 status is reported as suspended. Queue
2 transitions back to the active state when queue 1 becomes idle or paused.
A trigger pending state is required since both queues cannot be active at the same time. The status of queue
2 is changed to trigger pending when a trigger event occurs for queue 2 while queue 1 is active. In the
opposite case, when a trigger event occurs for queue 1 while queue 2 is active, queue 2 is aborted and the
status is reported as queue 1 active, queue 2 suspended. So due to the priority scheme, only queue 2 can
be in the trigger pending state.
There are two transition cases which cause the queue 2 status to be trigger pending before queue 2 is shown
to be in the active state. When queue 1 is active and there is a trigger pending on queue 2, after queue 1
completes or pauses, queue 2 continues to be in the trigger pending state for a few clock cycles. The
following are fleeting status conditions:
Figure 13-13
transition from queue 1 active to queue 2 active.
The queue status field is affected by the stop mode. Because all of the analog logic and control registers
are reset, the queue status field is reset to queue 1 idle, queue 2 idle.
13-26
•
•
Queue 1 idle with queue 2 trigger pending
Queue 1 paused with queue 2 trigger pending
displays the status conditions of the queue status field as the QADC64E goes through the
Figure 13-13. QADC64E Queue Status Transition
Idle (Paused)
Idle (Paused)
Queue 1
MPC561/MPC563 Reference Manual, Rev. 1.2
Active
Active
Trigger Pending
Trigger Pending
Queue 2
Active
Idle
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