MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 216
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
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Quantity:
10 000
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Part Number:
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Burst Buffer Controller 2 Module
4.3.2
The BBC also supports the enhanced external interrupt model of the MPC561/MPC563 which allows the
removal of the interrupt requesting a source detection stage from the interrupt routine. The interrupt
controller provides the interrupt vector to the BBC together with an interrupt request to the RCPU. When
the RCPU acknowledges an interrupt request, it issues an external interrupt vector to the BBC. The BBC
logic detects this address and replaces it with another address corresponding to the interrupt controller
vector, which is defined by the highest priority interrupt request from a peripherial module or external
interrupt request pin. See
The external interrupt relocation table should be placed at the physical address defined in the external
interrupt relocation table base address register. See
4-10
1
2
Implementation Dependent
Instruction Storage
Protection Error
Implementation Dependent
Data Storage Protection
Error
Implementation Dependent
Data Breakpoint
Implementation Dependent
Instruction Breakpoint
Implementation Dependent
Maskable External
Breakpoint
Non-Maskable External
Breakpoint
1
2
Refer to
0x500 is remapped if the EEIR feature is enabled. See
(EEIR).”
ISB offset is equal 4M * ISB (0x400000 * ISB), where ISB is value of bit field in USIU IMMR register.
This offset is different from the MPC555.
Name of Exception
Enhanced External Interrupt Relocation (EEIR)
0
0
1
1
Table
BBCMCR(OERC[0:1])
4-2.
Figure
Table 4-1. Exception Addresses Mapping (continued)
Table 4-2. Exception Relocation Page Offset
0
1
0
1
Original Address Issues by
MPC561/MPC563 Reference Manual, Rev. 1.2
4-3.
0xFFF0 1C00
0x0FFF 1D00
0xFFF0 1E00
0xFFF0 1F00
0xFFF0 1300
0xFFF0 1400
Core
0x3F E000 + ISB offset
0x1 0000 + ISB offset
0x8 0000 + ISB offset
Section 4.6.2.5, “External Interrupt Relocation Table
Section 4.3.2, “Enhanced External Interrupt Relocation
0x0 + ISB offset
Page Offset
Mapped Address by Exception Table
1
Page_Offset+0x0A0
Page_Offset+0x0E0
Page_Offset+0x0E8
Page_Offset+0x0F0
Page_Offset+0x0F8
Page_Offset+0x098
Relocation Logic
L-bus (CALRAM)
Freescale Semiconductor
Comments
512 Kbytes
64 Kbytes
Address
0
2
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