Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 249

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

Table 115. I2CSTATE_H
PS022008-0810
State Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
State Name
Idle
Slave Start
Slave Bystander
Slave Wait
Master Stop2
Master Start/Restart
Master Stop1
Master Wait
Slave Transmit Data
Slave Receive Data
Slave Receive Addr1
Slave Receive Addr2
Master Transmit Data
Master Receive Data
Master Transmit Addr1
Master Transmit Addr2
P R E L I M I N A R Y
State Description
I
I
Address did not match - ignore remainder of transaction.
Waiting for STOP or RESTART condition after sending a
Not Acknowledge instruction.
Master completing STOP condition (SCL = 1, SDA = 1).
Master mode sending START condition (SCL = 1, SDA =
0).
Master initiating STOP condition (SCL = 1, SDA = 0).
Master received a Not Acknowledge instruction, waiting
for software to assert STOP or START control bits.
Nine substates, one for each data bit and one for the
acknowledge.
Nine substates, one for each data bit and one for the
acknowledge.
Slave Receiving first address byte (7 and 10 bit
addressing)
Nine substates, one for each address bit and one for the
acknowledge.
Slave Receiving second address byte (10 bit
addressing)
Nine substates, one for each address bit and one for the
acknowledge.
Nine substates, one for each data bit and one for the
acknowledge.
Nine substates, one for each data bit and one for the
acknowledge.
Master sending first address byte (7- and 10-bit
addressing)
Nine substates, one for each address bit and one for the
acknowledge.
Master sending second address byte (10-bit addressing)
Nine substates, one for each address bit and one for the
acknowledge.
2
2
C bus is idle or I
C Controller has received a start condition.
2
C Controller is disabled.
I
2
C Master/Slave Controller
Product Specification
ZNEO
Z16F Series
233