Z16F2811AL20SG Zilog, Z16F2811AL20SG Datasheet - Page 127

• Manufacturer Part Number: Z16F2811AL20SG
• Description: IC ZNEO MCU FLASH 128K 100LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2811AL20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4533

PS022008-0810
Bit Position
[5–3]
PRES
[2–0]
TMODE[2:0]
Value (H) Description
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
000
001
010
011
100
101
110
111
The timer input clock is divided by 2
The prescaler is reset each time the timer is disabled. This ensures proper
clock division each time the timer is restarted.
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 128
This field along with the TMODE[3] bit in T0CTL0 register determines the
operating mode of the timer. TMODE[3:0] selects from the following modes: 
ONE-SHOT mode
CONTINUOUS mode
COUNTER mode
PWM SINGLE OUTPUT mode
CAPTURE mode
COMPARE mode
GATED mode
CAPTURE/COMPARE mode
PWM DUAL OUTPUT mode
CAPTURE RESTART mode
COMPARATOR COUNTER mode
TRIGGERED ONE-SHOT mode
PWM DUAL OUTPUT mode — If enabled, the timer output is set=TPOL
after PWM match and set = TPOL after Reload. If enabled the timer
output complement takes on the opposite value of the timer output. The
PWMD field in the T0CTL1 register determines an optional added delay
on the assertion (Low to High) transition of both timer output and the timer
output complement for deadband generation.
CAPTURE RESTART mode — If the timer is enabled, the timer output
signal is complemented after timer Reload.
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
ANALOG
the timer output signal is complemented after timer Reload.
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
TRIGGERED ONE-SHOT mode — If the timer is enabled, the timer
output signal is complemented after timer Reload.
0 = The timer triggers on a Low to High transition on the input.
1 = The timer triggers on a High to Low transition on the input.
P R E L I M I N A R Y
COMPARATOR COUNTER mode — If the timer is enabled,
PRES
, where PRES is set from 0 to 7.
Product Specification
ZNEO
Z16F Series
Timers
112